Maurice Meijer

On-chip digital power supply control for system-on-chip applications

The authors presented an on-chip, fully-digital, power-supply control system. The scheme consists of two independent control loops that regulate power supply variations due to semiconductor process spread, temperature, and chips workload. Smart power-switches working as linear voltage regulators are used to adjust the local power supply. The smart power-switch allows us to keep the global power network unchanged. It offers an integrated standby mode and has a fast dynamic response, i.e. low transition times between voltage steps at the cost of the reduced power conversion efficiency when compared to complex DC-DC converters.

Testing and diagnosis of power switches in SOCs

The use of power switches in modern system chips (SOCs) is inevitable as they allow for efficient on-chip static power management. Leakage is today one of the main hurdles in low-power applications. Power switches enable power gating functionality, i.e., one or more parts of the SOC can be powered-off during standby mode leading in this way to savings in the overall SOCs power consumption. In this paper, we present a circuit and a method to test power switches. The proposed method allows testing of on/off functionality. In case of segmented power switches individual failing segments can be identified as well by using the proposed test strategy. The method requires only a small number of test patterns that are easy to generate. Furthermore, the proposed method is very scalable with the number of power switches and has a very small area-overhead

Technology exploration for adaptive power and frequency scaling in 90nm CMOS

In this paper we examine the expectations and limitations of design technologies such as adaptive voltage scaling (AVS) and adaptive body biasing (ABB) in a modem deep sub-micron process. To serve this purpose, a set of ring oscillators was fabricated in a 90nm triple-well CMOS technology. The analysis hereby presented is based on two ring oscillators running at 822MHz and 93MHz, respectively. Measurement results indicate that it is possible to reach 13.8/spl times/ power savings by 3.4/spl times/ frequency downscaling using AVS, /spl plusmn/11% power and /spl plusmn/8% frequency tuning at nominal conditions using ABB only, 22/spl times/ power savings with 5/spl times/ frequency downscaling by combining AVS and ABB, as well as 22/spl times/ leakage reduction.

Limits to performance spread tuning using adaptive voltage and body biasing

We examine technology constraints on tuning active power and delay using adaptive voltage scaling (AVS) and adaptive body biasing (ABB) design techniques. To serve this purpose, a test circuit was fabricated in a 90 nm triple-well low-power CMOS technology. The presented analysis is based on a ring oscillator running at 488 MHz and a circular shift register with 8 K flip-flops and 50 K gates. Measurement results indicate that it is possible to reach 24.4/spl times/ power savings by 6.1/spl times/ frequency downscaling using AVS, /spl plusmn/24% power and /spl plusmn/22% frequency tuning at nominal conditions using ABB only, 127/spl times/ power savings with 37.4/spl times/ frequency downscaling by combining AVS and ABB.

Energy-Efficient FPGA Interconnect Design

Despite recent advances in FPGA devices and embedded cores, their deployment in commercial products remains rather limited due to practical constraints on, for example, cost, size, performance, and/or energy consumption. In this paper, we address the latter bottleneck and propose a novel FPGA interconnect architecture that reduces energy consumption without sacrificing performance and size. It is demonstrated that the delay of a full-swing, fully-buffered interconnect architecture can be matched by a low-swing solution that dissipates significantly less power and contains a mix of buffer and pass-gate switches. The actual energy savings depend on the specifics of the interconnect design and applications involved. For the considered fine-grain FPGA example, energy savings are observed to range from a factor 4.7 for low-load critical nets to a factor 2.8 for high-load critical nets. The results are obtained from circuit simulations in a 0.13mum CMOS technology for various benchmarks

Reducing Cross-Talk Induced Power Consumption and Delay

Coupling capacitances between on-chip wires dominate the power consumption of deep submicron busses. Opposite switching signals on adjacent lines cause additional power to be consumed and cause a crosstalk induced delay. This paper proposes a transition dependent skew on all the wires, such that opposite transitions do not occur simultaneously, but transitions in the same direction still do. An example is given how this can be realized with only simple coding circuitry. By inserting an intermediate state, this technique offers almost 25% savings of power on the bus lines, and a delay reduction of at least 5%. Larger reductions of the delay (upto 20%) are possible using a more aggressive repeater insertion scheme.

Modelling the dynamic response of on-chip decoupling capacitors

High-speed digital circuits require increasing amounts of on-chip decoupling capacitors (decaps) to preserve power integrity. Therefore, proper modelling and analysis of the dynamic response of such decaps in the high frequency range is needed. This paper shows that, in that range, lumped decap models fail and have to be substituted by distributed models. A derivation of such distributed model based on physical grounds is presented and compared with SPICE non-quasi static MOS models.

Glitch-free discretely programmable clock generation on chip

In this paper we describe a solution for a glitch-free discretely programmable clock generation unit (DPGC). The scheme is compatible with a GALS communication scheme in the sense that clock gating and clock pausing are possible. Besides, the proposed scheme does not require waiting for a new clock as the frequency change is seen as almost instantaneously. A prototype has been designed for a 0.13/spl mu/m triple-well CMOS process technology to also study the properties of the scheme with respect to voltage scaling.

Active noise cancellation using aggressor-aware clamping circuit for robust on-chip communication

As the IC process technology scales the on-chip wiring network becomes denser. Increasing aspect ratios of the on-chip interconnects lead to higher coupling capacitances and ultimately higher cross-talk noise, which degrades signal integrity. In this paper we propose a clamping circuit for on-chip busses, which clamps a victim wire in an on-chip bus based on the states of its immediate aggressors. These clampers help the driver of the victim wire in draining the charge, which is induced due to cross-talk between aggressors and victim wires. This helps in decreasing the cross-talk peak noise and also the delay variability (referred to as delay noise). Simulation results for a 10 mm long communication bus (parallel wires) laid at minimum pitch in 0.13 /spl mu/m CMOS technology show that a reduction of 30%(17.6%), 37%(27.2%) and 26%(65.8%) in cross-talk peak noise amplitude (delay noise) is observed for point to point, parallel repeater inserted and staggered repeater inserted respectively when only immediate neighbours are considered (1/sup st/ order). Furthermore the aggressor-aware clamper is very effective in avoiding glitches, which may occur when more aggressors, in addition to the immediate ones are also switching simultaneously in the same.

A Voltage-Mode Testing Method to Detect IDDQ Defects in Digital Circuits

A novel method to detect a defective IDDQ on top of highbackground current is proposed. Instead of the conventionalapproach that measures the quiescent current drawn by thecircuit-under-test (CUT), the proposed method is based on themeasurement of the voltage drop in a resistor spatially laid-outalong the CUT. Resistive shorts with a defective current of 2.14 mAon top of 83.11 mA of leakage current have been detected in a65nm CMOS test chip with controllable leakage. The proposedmethod also provides facilities to locate the defect in addition to detect it.