Nigel R. Farrar

Fabrication of 0.1-um T-shaped gates by phase-shifting optical lithography

We have developed a method for patterning sub-micrometer gates with T-shaped cross sections, which may be applied to manufacture high performance field effect transistors (FETs). The technique employs two exposures at the KrF excimer laser wavelength (248 nm). The first exposure uses a phase-shifting mask to pattern 0.1 micrometers isolated spaces. The resist used for the second exposure absorbs the 248 nm radiation strongly enough to produce a profile suitable for lift-off patterning.

Laser-Assisted TiSi 2 Formation for ULSI Applications

In this paper, we describe the results of recent work in which TiSi 2 formation on deep-submicron polysilicon gates is achieved using pulsed excimer laser irradiation. Formation of low resistivity titanium suicide on sub-0.1 μm polysilicon lines is confirmed by sheet resistance measurements. High-resolution TEM examination shows exceptionally smooth interface between suicide and heavily-doped silicon substrate. Gate to source/drain bridging is not observed. Analytical techniques including Rutherford backscattering spectroscopy (RBS) and X-ray diffraction (XRD) have been used to characterize the irradiated films. This laser-assisted suicide formation process is a promising technology for extreme submicron MOSFET applications.

Effect of off-axis illumination on stepper overlay

Modified illumination schemes for wafer steppers, such as oblique and low partial coherence illumination, can improve the imaging performance for some types of microlithography patterns. Implementation of these methods by simple insertion of apertures into a stepper illuminator, without reoptimization of the illuminator, can lead to deterioration in illumination power and uniformity. The different apertures may also affect lens aberrations, lens distortion and illumination telecentricity and require adjustments for the effective control of dose, focus and reduction ratio. This study has examined the set-up of a modified illumination system, the effects of four different illuminator apertures on several lens parameters and the consequent effect on overlay between layers printed with different apertures. It is found that the lens performance is either not significantly changed or can be compensated adequately in the case of off-axis illumination apertures but deteriorates when using low partial coherence illumination. However, preliminary overlay tests between fields printed using different apertures show acceptable performance in all cases.

Real-time amine monitoring and its correlation to critical dimension control of chemically amplified resists for sub-0.25-μm geometries

One such issue is the quantitative control of critical dimension (CD) and how to calibrate fab contamination levels to linewidth control. Since most fabs build several generations of devices, contamination levels for older generations may not be suitable for new generations. Therefore, studies to control CD for each generation are required to determine the effectiveness of filtration schemes. In this paper the authors have investigated CD control for imaging dimensions from 0.25 micrometers to 0.15 micrometers . We have also correlated this data back to chemical monitoring levels to determine CD vs. PED stability for these geometrys to determine the contamination level tolerance. Additionally, the authors have generated process windows to determine the effect such delays have on process windows.

Performance of through-the-lens/off-axis laser alignment systems and alignment algorithms on Nikon wafer steppers

New generations of ULSI devices require significant improvements in circuit overlay. The performance limits of a current wafer stepper alignment system have been evaluated by testing alignment target capture on planarized targets and rough substrates. Although new hardware is being developed for alignment under difficult conditions, it has been shown that new algorithm designs can extend the performance of existing systems.

Comparisons of critical parameters for high- and low-activation-energy deep-UV photoresists

A major factor in the substantial improvement in the performance and environmental stability of DUV chemical amplified resists involved a change in the chemistry of the protecting group. A divergence of resist design has recently occurred, leading to two completely different resist classes, each with its promises and problems. These new resists (once again based on hydroxystyrene copolymers and terpolymers) can be grouped by activation energy. In this paper the authors will attempt to answer these questions and perhaps highlight areas of additional concern. Results from our investigations of two photoresists of either high or low activation energy system will be presented. Critical parameters such as overall process windows for sub-200 nm lithography variation with PEB temperature (linewidth/ degree(s)C), PEB delay, line slimming, etch rates and bottle stability will be discussed.

Can we do 0.15µm lithography with KrF

Deep-UV lithography using 248 and 193-nm light will likely be the microlithography technology of choice for the manufacture of advanced memory and logic semiconductor devices for the next decade. Since 193nm lithography development has been slow, the extension of 248nm technology to 150nm and beyond is required. Advanced techniques, such as Optical Proximity Correction (OPC) and Phase Shift Masks (PSM) will be needed in order to maintain sufficient process latitude. This paper will discuss recent work to investigate the capability of 248nm lithography at 150nm. Imaging results using conventional and off-axis illumination (OAI) will be presented. Key resist performance parameters will be discussed, including process latitude, linewidth and line length control and full field critical dimension (CD) control. Although the performance appears to be adequate for early process and device development, further enhancements will be required for a manufacturable process at 150nm.

Linewidth control for 0.25 micron gate patterning

Linewidth control of small lines over non-planarized topography is particularly challenging due to resist thin film interference effects and reflective notching. This paper compares the linewidth control performance of several deep-UV resist processes, using dyed resist and both top and bottom anti-reflection coatings. Only the bottom anti-reflective coating (BARC) provides adequate linewidth control for development work on 0.25 micron gate patterning. The BARC and resist coating behavior over isolation topography is characterized using atomic force microscopy and correlated to residual linewidth variation. The performance of a zero bias etch process for BARC removal is also presented.

Photolithography process characterization and 3D simulation using track-mounted development rate monitor data

A track-mounted, in-situ dissolution rate monitor (DRM) is used to study the impact of exposure variations on g-line, i-line and DUV positive chemically amplified resists. In the i- line case, a comparative study between constant spray and a spray/puddle process was undertaken. In all cases, modeling parameters were extracted from the track-mounted DRM data and entered into 2D and 3D simulators using an experimentally generated development rate vs. PAC concentration table. Simulated profiles were compared with actual SEM cross- sections. Whenever possible, DRM traces were used to analyze standing waves, surface inhibition effects and quantify resist performance by calculating contrast. For the g-line case, the impact of PEB temperature upon the standing wave effects, as quantified by the in-situ DRM data, was studied.

Process engineering: overview of wafer fab process engineering dealing with equipment, processes, and control techniques to meet the SIA road map

Lithography process control is critical for achieving good yield from increasingly complex generations of integrated circuits. Linewidth and overlay control over large die areas are required with smaller errors than ever before. Increasingly complex and expensive equipment and processes are needed to meet these goals. This paper will give an overview of the process engineering issues primarily associated with the 0.35 micron and 0.25 micron generations of integrated circuits. Linewidth control, in particular, will be covered in some detail with emphasis on the effect of the different contributions to focus and exposure variations during patterning. The influence of incoming wafer process variations on the process design for different layers will be described. The challenges of defect density control and throughput and cost control using advanced equipment and processes will be outlined. Mask layout and fabrication issues relating to improved wafer process margins will be discussed. The impact of metrology limitations on the ability to control lithography processes will be described.