Hua-Yu Liu

Use of short-loop electrical measurements for yield improvement

Modern submicron processes are more sensitive to both random and systematic wafer-level process variation than ever before. Given the dimensional control limitations of new technologies, the amount of wafer-to-wafer and within wafer nonuniformity of many steps is becoming a significant fraction of the total error budget, which already includes the usual step-to-step allocations. However, a significant portion of the total observed variability is systematic in nature. Accordingly, particle defects may not continue to dominate parametric yield loss without improved understanding of parametric variations. In this paper, we demonstrate the use of short-loop electrical metrology to carefully characterize and decouple wafer-level variability of several critical processing steps. More specifically, we present our method and give results obtained from variability analyses for lithography critical dimension (CD) and inter-level dielectric (ILD) thickness control. Using statistically designed experiments and dedicated test structures, the main factors affecting dielectric thickness variability has been identified. The systematic variability from a wafer stepper has been extracted using a physically based statistical data filter. Once isolated, the deterministic variability can be modeled and controlled to enhance process and circuit design for manufacturability (DFM). We hope that in the future this work will be coupled with novel DFM-oriented CAD tools that encapsulate this information in a fashion that makes it useful to process and circuit designers. >

Fabrication of 0.1-um T-shaped gates by phase-shifting optical lithography

We have developed a method for patterning sub-micrometer gates with T-shaped cross sections, which may be applied to manufacture high performance field effect transistors (FETs). The technique employs two exposures at the KrF excimer laser wavelength (248 nm). The first exposure uses a phase-shifting mask to pattern 0.1 micrometers isolated spaces. The resist used for the second exposure absorbs the 248 nm radiation strongly enough to produce a profile suitable for lift-off patterning.

Contributions of stepper lenses to systematic CD errors within exposure fields

We have studied systematic line width (CD) errors as functions of field coordinates for three late-model i-line steppers from different manufacturers by measuring electrical resistance of lines patterned in poly-silicon. The combination of reticle errors with non-linear imaging accounts for a significant fraction of the total line width errors. After removing the effects of reticle errors, CD contour maps are consistent with aberration patterns in which the Strehl intensity is highest at the center of the field.

A statistically based model of electron‐beam exposed, chemically amplified negative resist

A methodology based on statistically designed factorial experiments has been developed to model the dissolution rate of an electron‐beam exposed chemically amplified resist, Shipley SAL‐601‐ER7, for different post‐exposure bake (PEB) and developer concentrations. A statistical experiment of dissolution rate measurements were performed in the Perkin‐Elmer development rate monitor using a central composite design with PEB temperature, PEB time, and developer concentration as the factors. These measurements were combined with Monte Carlo simulation of electron energy deposition to generate dissolution rate data as a function of absorbed energy. These data were then fitted to a semiempirical rate equation using nonlinear regression. Statistical analysis of the effects of the three processing factors on the parameters of the rate functions yielded empirical models relating the parameters to the factors. As a result, a rate equation can be determined for any processing conditions, and thus a complete model is o...

Patterning tool characterization by causal variability decomposition

A spatial and causal classification of process error provides opportunities for the accurate determination and efficient management of process error budget. Traditional metrology is posed with this dilemma: variability sampling requires cheap, highly repeatable metrology, such as electrical measurements, which also confound error sources of the variability sampled. In response, statistical metrology has been proposed as a novel combination of cost-effective metrology with subsequent statistical or experimental data processing to provide a technique that is capable of error decomposition into equipment causes. The methodology, consisting of 1) reticle and experiment design, 2) data filtering, and 3) error budget formulation, is presented and is general to a short-loop thin-film patterning sequence. A .35-/spl mu/m polygate patterning sequence is chosen to demonstrate this technique. Reticle design and statistical filtering have been presented in a previous publication, and are summarized here. The second causal data filter is presented in this work, Aided by additional experimentation, a physical filter decomposes the separate contributions and interactions of the reticle and stepper. A portion of the error budget is calculated, including the effects of spatial correlation. The results of decomposition yields a numerical metric for equipment and process manufacturability. Results are presented that illustrate the use of the manufacturability metric in equipment selection and process design.

Intrafield linewidth variances in 0.25 μm i‐line lithography

We have studied variations of the widths of polysilicon lines patterned to nominal dimensions of 0.25 μm with an i‐line stepper. The analysis is based on measurements of electrical resistance of the etched polysilicon patterns. Systematic dependence of linewidths on exposure field coordinates accounts for a large fraction of their total variance. We have expressed the systematic intrafield variance as a sum of three terms: one attributed to the stepper, another to the reticle, and a third to both. The systematic intrafield dependence is most significant for small isolated lines; this term alone had a 3σ value of 25 nm at a nominal dimension of 0.25 μm.

100-nm CMOS gates patterned with 3 sigma below 10 nm

We have developed a process that uses a series of depositions and etches to pattern poly-silicon gates, eliminating the component of line width variation that normally arises from photolithography. Because the depositions and etches that determine line width are well controlled, we can pattern finer lines with better control using this process than with conventional methods. The results presented here show 3(sigma) < 10 nm for 100 nm lines. They are consistent with requirements for patterning gates in 2006 according to the 1997 edition of the National Technology Roadmap for Semiconductors. Using this patterning technique, we have made 100 nm nMOS transistors with 2 nm thick gate oxide, operating at 1.3 V. The distributions of important variables that characterize the operation of these transistors are shown to be much tighter than we obtain with conventional lithography.

Comparisons of critical parameters for high- and low-activation-energy deep-UV photoresists

A major factor in the substantial improvement in the performance and environmental stability of DUV chemical amplified resists involved a change in the chemistry of the protecting group. A divergence of resist design has recently occurred, leading to two completely different resist classes, each with its promises and problems. These new resists (once again based on hydroxystyrene copolymers and terpolymers) can be grouped by activation energy. In this paper the authors will attempt to answer these questions and perhaps highlight areas of additional concern. Results from our investigations of two photoresists of either high or low activation energy system will be presented. Critical parameters such as overall process windows for sub-200 nm lithography variation with PEB temperature (linewidth/ degree(s)C), PEB delay, line slimming, etch rates and bottle stability will be discussed.

Impact of photomasks on linewidth variation

In modern logic processes, variation of linewidths, rather than resolution, often sets the practical lower limit to dimensions. In this context, it is useful to understand how linewidth errors on photomasks contribute to linewidth errors on silicon. It is generally impossible to express the total linewidth variance as the sum of terms that depend only on the photomask or only on other factors. This follows partly because linewidth errors from several sources, such as non- uniform illumination or aberrations of the projection optics, combine with photomask errors to yield significant covariance. In this regard, photomask errors characterized by low spatial frequencies, such as those arising from resist and Cr processing, are more significant than the errors mask writers produce with higher spatial frequencies. A further complication at dimensions of interest, is that printed linewidth is a non-linear function of photomask linewidth, the effect being to amplify the consequences of linewidth errors on photomasks. Closely related to non-linearity are line shortening and proximity effects. When photomasks are compensated to mitigate these problems, round-off to minimum address increments becomes another source of linewidth errors.

Can we do 0.15µm lithography with KrF

Deep-UV lithography using 248 and 193-nm light will likely be the microlithography technology of choice for the manufacture of advanced memory and logic semiconductor devices for the next decade. Since 193nm lithography development has been slow, the extension of 248nm technology to 150nm and beyond is required. Advanced techniques, such as Optical Proximity Correction (OPC) and Phase Shift Masks (PSM) will be needed in order to maintain sufficient process latitude. This paper will discuss recent work to investigate the capability of 248nm lithography at 150nm. Imaging results using conventional and off-axis illumination (OAI) will be presented. Key resist performance parameters will be discussed, including process latitude, linewidth and line length control and full field critical dimension (CD) control. Although the performance appears to be adequate for early process and device development, further enhancements will be required for a manufacturable process at 150nm.