Carl P. Babcock

Double dipole RET investigation for 32 nm metal layers

For 32 nm test chips, aggressive resolution enhancement technology (RET) was required for 1x metal layers to enable printing minimum pitches before availability of the final 32 nm exposure tool. Using a currently installed immersion scanner with 1.2 numerical aperture (NA) for early 32 nm test chips, one of the RET strategies capable of resolving the minimum pitch with acceptable process latitude was dipole illumination. To avoid restricting the use of minimum pitch to a single orientation, we developed a double-expose/single-develop process using horizontal and vertical dipole illumination. To enable this RET, we developed algorithms to decompose general layouts, including random logic, interconnect test patterns, and SRAM designs, into two mask layers: a first exposure (E1) of predominantly vertical features, to be patterned with horizontal dipole illumination; and, a second exposure (E2) of predominantly horizontal features, to be patterned with vertical dipole illumination. We wrote this algorithm into our OPC program, which then applies sub-resolution assist features (SRAFs) separately to the E1 and E2 masks, coordinating the two to avoid problems with overlapping exposures. This was followed by two-mask OPC, using E1 and E2 as mask layers and the original layout (single layer) as the target layer. In this paper, we describe some of the issues with decomposing layout by orientation, issues that arise in SRAF application and OPC, and some approaches we examined to address these issues.

Can we do 0.15µm lithography with KrF

Deep-UV lithography using 248 and 193-nm light will likely be the microlithography technology of choice for the manufacture of advanced memory and logic semiconductor devices for the next decade. Since 193nm lithography development has been slow, the extension of 248nm technology to 150nm and beyond is required. Advanced techniques, such as Optical Proximity Correction (OPC) and Phase Shift Masks (PSM) will be needed in order to maintain sufficient process latitude. This paper will discuss recent work to investigate the capability of 248nm lithography at 150nm. Imaging results using conventional and off-axis illumination (OAI) will be presented. Key resist performance parameters will be discussed, including process latitude, linewidth and line length control and full field critical dimension (CD) control. Although the performance appears to be adequate for early process and device development, further enhancements will be required for a manufacturable process at 150nm.