Nikhil Raj

Low power high output impedance high bandwidth QFGMOS current mirror

Current mirror is a basic block of any mixed-signal circuit for example in an analog-to-digital converter. Its precise performance is the key requirement for analog circuits where offset is a measure issue. The key parameter which defines the performance of current mirror is its input/output impedance, input swing, and bandwidth. In this paper, a low power design of current mirror using quasi-floating gate MOS transistor is presented. The proposed current mirror boosts its output impedance in range of giga-ohm through use of regulated cascode structure followed by super-cascode. Another improvement is done in reduced input compliance voltage limits with the help of level shifter. The proposed current mirror operates well for input current range 0-700@mA with an input and output impedance of 160@W and 8.55G@W respectively and high bandwidth of 4.05GHz. The total power consumption of the proposed current mirror is about 0.84mW. The low power consumption with enhanced output impedance and bandwidth suits proposed current mirror for various high-speed analog designs. Performance of the presented current mirror circuit is verified using HSpice simulations on 0.18@mm mixed-mode twill-well technology at a supply voltage of +/-0.5V.

Design of reversible multiplexer/de-multiplexer

Reversible logic is an emerging technique of upcoming future technologies. Low heat dissipation and energy recycle principle are encouraging its demand for low power daily usage portable devices. In this paper, two reversible gates have been proposed, named as R-I gate and R-II gate, for realizing reversible combinational logic circuits. The proposed two gates can be used for realisation of basic logical functions such as AND, XOR, MUX etc. Besides these functions, other advantage of the proposed R-I gate is that it can be used as a 1:2 de-multiplexer without requiring any extra logic circuits and the proposed R-II gate can be used as a half adder circuit. The proposed reversible gates are implemented and verified using Xilinx ISE 10.1 software. The simulation results show that the proposed designs are more efficient in terms of gate count, garbage outputs and constant inputs than the existing reversible logic gate.

An effective design technique to reduce leakage power

Now a days low power Design is a essential requirement for This electronic document is a “live” template. The various components of your paper [title, text, heads, etc.] are already defined on the style hardware implementation. Technology moving into deep submicron region causes increase in leakage power. MTCMOS is promising technique for reducing leakage power but use of this technique results in delay overhead in active mode and data retention problem for sequential circuit. This paper propose a design technique for reducing the leakage power and data loss problem during sleep mode. Simulation results show that reduction in leakage power while preserving the state of the circuit.

Modeling of Human Voice Box in VLSI for Low Power Biomedical Applications

Abstract Communication is heavily dependent on ideas expressed through speech. The ideas and tonal qualities during vocal expression give voice an idea about person characteristics and personality. The estimation of vocal tract configuration from speech sound to represent speech events with robust and compact signals that describe the salient features of speech is an important area of speech communication. The Human Voice Box (Glottis) is the source of voice production and an important part of human body. Recent techniques of speech processing, such as speech recognition and speech synthesis, use the glottal closure and opening instants. Current models of the glottal waves derive their shape from approximate information rather than from exactly measured data. In this work, an electrical model of Human Voice Box is presented by exploiting fluid volume velocity to current and fluid pressure to voltage. The glottis modeled as current source includes linear and nonlinear impedances to represent laminar and turbulent flow, respectively, in the vocal tract. The complete model of glottis runs at power supply of 1.8 volt and the design is verified in a standard TSMC 0.18 micrometer technology on BSIM 3v3 model using ELDO Simulator.

Bulk driven OTA in 0.18 micron with high linearity

Operational Transconductane Amplifier (OTA) is a fundamental building block of analog signal processing application. This paper demonstrates a wide-linear-range low voltage subthreshold-mode based fully differential OTA using bulk-driven technique. The proposed OTA is linearly tunable with the feature of low distortion and high output impedance. The open loop gain of OTA is enhanced through use of improved Wilson current mirror. The OTA provides an increase in its linearity to about ± 1.9 volt. The open loop gain is enhanced to 65dB at unity gain bandwidth (UGB) of 609.46 KHz. The proposed OTA operates at 0.9 volts and power consumption of the OTA remains in range of few hundreds of nanowatts. The OTA analysis has been performed in a standard TSMC 0.18 micrometer technology on BSIM 3v3 model using ELDO Spice Simulator.

A Low Voltage High Performance OTA in 0.18 Micron with High Linearity

The increasing demand of personal health monitoring products with long battery life had forced designers to use of those circuits which consumes low power. Operational Transconductance Amplifier (OTA) operating in subthreshold (weak inversion) region introduces a versatile solution for the realization of low power VLSI building blocks. This paper demonstrates a modified OTA with high linearity and better performance achieved by using High-swing improved-Wilson current mirror for low power and low-frequency applications. The achieved linearity is about ± 1.9 volt and unity gain bandwidth (UGB) of 342.30 KHz. The OTA is operated at power supply of 0.9 volt and consumes power in range of nanowatts. The OTA simulation has been performed in a standard TSMC 0.18 micrometer technology on BSIM 3v3 model using ELDO Simulator.

High performance current mirrors using quasi-floating bulk

In this paper, a modified structure of standard MOSFET is proposed which offer high transconductance in comparison to its conventional architecture. The conventional MOSFET is a four terminal device whose fourth terminal, the bulk is connected to either negative/positive supply for N-channel/P-channel transistor respectively, or to their source terminal. In the proposed structure, instead of connecting bulk to supply rails or to source terminals, the bulk is configured in a quasi-floating state and then connected back to its gate terminal. The resultant is a gate driven quasi floating bulk MOSFET. Under DC analysis, the proposed structure operates as standard gate driven MOSFET whereas performing analysis in frequency domain the structure results in effective transconductance higher than that of standard MOSFET. Using the proposed structure, three high performance current mirrors are presented in this paper which showed improved performance over its conventional architectures. Performance of the proposed structure and the current mirror circuits are verified using HSpice simulations on 0.18źm mixed-mode twin-well technology at a supply voltage of ź0.5V.

Low voltage high performance bulk driven quasi-floating gate based self-biased cascode current mirror

A low voltage high performance self-biased cascode current mirror in terms of output resistance and bandwidth is proposed in this paper. The proposed current mirror enhances the output resistance in range of mega ohms and also shows a significant improvement in bandwidth compared to prior arts. The current mirror is designed using bulk-driven technique which helps it to operate at very low supply voltage of ź 0.2V. To achieve high output resistance, the proposed current mirror uses the super cascode stage at its output. Furthermore, an external capacitor is used which accounts for increasing the bandwidth. Small-signal analysis carried proves the improvement achieved by proposed architecture. The current mirror operates well for wide input current range from 0 to 200 µ A with good linearity and shows the bandwidth of 415MHz. The observed input and output resistance is 300ź and 212Mź respectively. Further, the THD and mismatch analysis is carried to prove the robustness of proposed current mirror. The complete analysis of proposed current mirror is shown using HSpice simulations on UMC 0.18µm technology.

MOS Modelling and Simulation of Human Glottis

The problem of representing speech events with robust and compact signals that describe the salient features of speech is an important area of speech communication. The Glottal Source is an important component of voice as it can be considered as the excitation signal to the voice apparatus. Nowadays, new techniques of speech processing such as speech recognition and speech synthesis use the glottal closure and opening instants. The pitch synchronous analysis that is used in several area of speech processing often requires robust detection of the instants of glottal closure and opening. Current models of the glottal waves derive their shape from approximate information rather than from exactly measured data. General method concentrate on assessment of the glottis opening using optical, acoustical methods, or on visualization of the larynx position using ultrasound, computer tomography or magnetic resonance imaging techniques. In this work, an experimental integrated circuit of human glottis using MOS is presented by exploiting fluid volume velocity to current, fluid pressure to voltage, and linear and nonlinear mechanical impedances to linear and nonlinear electrical impedances. The glottis modeled as current source includes linear, non-linear impedances to represent laminar and turbulent flow respectively, in vocal tract. The MOS modeling and simulation of glottis were carried out on TSMC 0.18 micrometer technology.

Circuit-Level Design of Human Voice Source

Communication is heavily dependent on ideas expressed through speech. The ideas and tonal qualities during vocal expression give voice an idea about person characteristics and personality. The problem of representing speech events with robust and compact signals that describe the salient features of speech is an important area of speech communication. The Glottal Source is an important component of voice as it can be considered as the excitation signal to the voice apparatus. Nowadays, new techniques of speech processing such as speech recognition and speech synthesis use the glottal closure and opening instants. The pitch synchronous analysis that is used in several area of speech processing often requires robust detection of the instants of glottal closure and opening. Current models of the glottal waves derive their shape from approximate information rather than from exactly measured data. General method concentrate on assessment of the glottis opening using optical, acoustical methods, or on visualization of the larynx position using ultrasound, computer tomography or magnetic resonance imaging techniques. In this work, an experimental integrated circuit of human glottis using MOS is presented by exploiting fluid volume velocity to current, fluid pressure to voltage, and linear and nonlinear mechanical impedances to linear and nonlinear electrical impedances. The glottis modeled as current source includes linear, non-linear impedances to represent laminar and turbulent flow respectively, in vocal tract. The MOS modeling and simulation of glottis were carried out on TSMC 0.18 micrometer technology.