Viraj A. Patwardhan

Solder joint reliability model vath modified Darveaux's equations for the micro smd wafer level-chip scale package family

Historically, energy-based solder fatigue lie models have been used primarily for PBGA or similar package configurations. In this paper, we extend the energy-based method to newly emerged Wafer Level, Chip Scale Package (WL-CSP). National Semiconductor’s micro SMD package family was chosen as the test vehicle. Among all energybased methods, Darveaux’s model is arguably the most popular one due to its well-documented good correlation with the actual tests. To maintain consistency in results, Darveaux suggested that the solder joint be meshed such that the element size in its height direction has fixed value. However, we found in our study that Darveaux’s model faired poorly in capturing the package fatigue life, even though the mesh size issue was carefully addressed. In view of the drastic difference in solder ball size between WL-CSP and PBGA, on which Darveaux’s model is based, we argue that in addition to the element size in the solder height direction, the f~te element calculation of inelastic dissipation may also depend on other meshing parameters, which may vary depending on the specific geometry of the solder bump. Consequently, we proposed a revised empirical equation to calculate the package fatigue life for micro SMD. The new equation is derived from correlating the simulation results with the test data. We also demonstrated that the new equation was capable of achieving a similar accuracy level as compared with Darveaux’s model for PBGA packages. The study also provided for the first time a good parametric model scalable to larger micro Sh4D VO count. In addition, the impact of different modeling schemes was also evaluated in terms of their accuracy and eficiency.

A parametric solder joint reliability model for wafer level-chip scale package

The micro-SMD is a Wafer Level-Chip-Scale Package (WL-CSP) designed to have external dimensions equal to that of the silicon device. This new package type extends flip-chip packaging technology to standard surface mount technology. The package has been successfully targeted for low pin count (less than 30), high volume applications such as cellular phones, hand-held PDAs, etc. Since the WL-CSP is typically used without underfill, solder joint reliability is of prime concern. A good understanding of the device failure mechanism when assembled on different board configurations is critical to the development of an accurate predictive model of solder fatigue. This paper presents results of a joint effort to develop a parametric predictive model of the solder joint reliability of the micro-SMD subjected to thermo-mechanical stresses. An 18 I/O micro-SMD was used as the primary test vehicle for the thermal cycling and thermal shock tests performed with different ramp/hold profiles. The parametric model developed can be extended to different pin count and die size of WL-CSPs with eutectic solder.

Lead-free wafer level-chip scale package: assembly and reliability

This paper discusses the reliability testing results of a lead-free version of the micro SMD, National Semiconductors Wafer Level-Chip Scale Package (WL-CSP). The micro SMD, a true wafer scale package has proven to be highly adaptable in the conventional assembly process, requiring no special considerations during the surface mount assembly operation. The current micro SMD utilizes standard Sn/Pb solder bumps as the interconnect medium. Based on evaluations of the various options available for the lead-free solder, micro SMD devices bumped with Sn/Ag/Cu solder were tested during this evaluation. There are two bump sizes currently available for the micro SMD package, a 170-micron bump diameter and a 300-micron bump diameter. This paper addresses the impact of board assembly conditions, package solder type, package bump size, and thermal cycling profiles on the reliability of the lead-free WL-CSPs. This paper will address the initial evaluations on the 170-micron bumped micro SMD packages. Results of this work are used to determine viable combinations of lead-free and eutectic solder. The lead-free version of the micro SMD is in synch with the next packaging evolutionary stage toward a lead-free assembly process.