Nima Karimpour Darav

Detailed placement accounting for technology constraints

Circuit placement involves the arrangement of a large number of cells which must be aligned to sites in rows without overlap. Placement is done via a sequence of optimization steps which include global placement, legalization and detailed placement. Global placement determines a rough position for each cell throughout the chip while optimizing objectives such as wirelength and routability. The rough placement is legalized and cells are aligned to sites in rows without overlap. Detailed placement attempts to further improve the placement while keeping the placement feasible. In reality, the placement of cells is more complicated than aligning cells to sites without overlap; detailed routability issues compound the placement problem by introducing issues such as pin shorts, pin access problems, and other spacing requirements. The importance of addressing these issues were highlighted during the recent ISPD2014 placement contest [1]. In many cases, detailed routability issues can be addressed during placement to avoid later problems. We describe our ISPD2014 contest legalizer and detailed placer (plus additional extensions) that can address many detailed routing issues without negatively impacting the quality of the final placement. Numerical results are presented to demonstrate the effectiveness of our techniques.

Eh?Placer: A High-Performance Modern Technology-Driven Placer

The placement problem has become more complex and challenging due to a wide variety of complicated constraints imposed by modern process technologies. Some of the most challenging constraints and objectives were highlighted during the most recent ACM/IEEE International Symposium on Physical Design (ISPD) contests. In this article, the framework of Eh?Placer and its developed algorithms are elaborated, with the main focus on modern technology constraints and runtime. The technology constraints considered as part of Eh?Placer are fence region, target density, and detailed routability constraints. We present a complete description on how these constraints are considered in different stages of Eh?Placer. The results obtained from the contests indicate that Eh?Placer is able to efficiently handle modern technology constraints and ranks highly among top academic placement tools.

High Performance Global Placement and Legalization Accounting for Fence Regions

The placement problem has become challenging due to a variety of complicated constraints imposed by modern process technologies. Some of the most challenging constraints were highlighted during the ISPD 2015 placement contest and include fence region and target density constraints; these constraints are in addition to those issues that affect detailed routability such as pin shorts, pin access problems and cell spacing issues. These constraints not only make cell placement more difficult, but can impact the placement objectives such as wire length, routability and so forth. In this paper, we present a comprehensive technique to address fence region constraints in global placement and legalization while still considering detailed-routing issues. We combine concepts from image processing such as region coloring with parallel programming to efficiently deal with fence regions. We also introduce a heuristic method to adjust target densities while avoiding adverse effects on the quality of global routability. Numerical results using both the released and hidden benchmarks from the ISPD 2015 placement contest demonstrate the efficacy of our proposed techniques.

A Detailed Routing-Aware Detailed Placement Technique

In this paper we propose a detailed placement algorithm targeting detailed rout ability for designs at or smaller than 22nm. The sheer number and complexity of routing design rules at these feature sizes preclude direct incorporation of detailed routing rules into a placement algorithm. However, using the detail routing information to guide the placement can significantly reduce the overall design time and improve the performance of the circuit. Our proposed detailed routing-aware detailed placement (DrDp) is developed as an add-on to the detailed placement process to improve detailed rout ability in a relatively short runtime. The proposed technique is added to the code obtained from one of the top three teams in the ISPD 2014 detailed routing-driven placement contest and tested on ISPD 2014 benchmark suite. Numerical results show that the proposed technique can improve the detailed routing quality with no significant change in detailed placement score, total wire length or runtime.

Detailed routing violation prediction during placement using machine learning

The complexity of design rules at 22nm and below precludes direct incorporation of detailed routing (DR) rules into a placement algorithm. However, ignoring routability rules during the placement process may result in infeasible designs. The congestion estimated by a global router is conventionally used for routing estimation during placement, but it does not include real detailed routing violations, which adversely affect the routability of a design. Presently, there are no methods that directly aim to predict detailed routing violations. In this paper we propose a machine learning based method to predict the shorts that are a major component of detailed routing violations. The proposed method can be integrated into a placement tool and be used as a guide during the placement process to reduce the number of shorts happening in the detailed routing stage. Empirical results show that our method is successful in predicting 88% of the shorts with only 16% incorrectly predicting shorts in no short violation area.

A Fast, Robust Network Flow-based Standard-Cell Legalization Method for Minimizing Maximum Movement

The standard-cell placement legalization problem has become critical due to increasing design rule complexity and design utilization at 16nm and lower technology nodes. An ideal legalization approach should preserve the quality of the input placement in terms of routability and timing, as well as effectively manage white space availability and have low runtime. In this work, we present a robust legalization algorithm for standard cell placement that minimizes maximum cell movements fast and effectively based on a novel network-flow approach. The idea is inspired by path augmentation but with important differences. In contrast to the classical path augmentation approaches, we resolve bin overflows by finding several candidate paths that guarantee realizable (legal) flow solutions. In addition, we show how the proposed algorithm can be seamlessly extended to handle relevant cell edge spacing design rules. Our experimental results on the ISPD 2014 benchmarks illustrate that our proposed method yields 2.5x and 3.3x less maximum and average cell movement, respectively, and the runtime is significantly (18x) lower compared to best-in-class academic legalizers.

Routing-Aware Incremental Timing-Driven Placement

Meeting timing requirements and improving routability are becoming more challenging in modern design technologies. Most timing-driven placement approaches ignore routability concerns which may lead to a gap in routing quality between the actual routing and what is expected. In this paper, we propose a routing-aware incremental timing-driven placementtechnique to reduce early and late negative slacks while considering global routing congestion. Our proposed flow considers both timing and routing metrics during the detailed placement. We also presents a comprehensive analysis of timing quality score and the total number of routing overflows and the trade-off between them by modifying the International Conference on Computer Aided Design (ICCAD) 2015 timing-driven contest benchmarksand the displacement constraints. Experimental results on the ICCAD 2015 Incremental Timing-Driven Contest benchmarks show the efficacy of our proposed routing-aware incremental timing-driven placement method. On average, we obtain 22% and 17% improvement in timing quality score and global routing overflows, respectively, compared to the first placed team at 2015 ICCAD contest.

A machine learning framework to identify detailed routing short violations from a placed netlist

Detecting and preventing routing violations has become a critical issue in physical design, especially in the early stages. Lack of correlation between global and detailed routing congestion estimations and the long runtime required to frequently consult a global router adds to the problem. In this paper, we propose a machine learning framework to predict detailed routing short violations from a placed netlist. Factors contributing to routing violations are determined and a supervised neural network model is implemented to detect these violations. Experimental results show that the proposed method is able to predict on average 90% of the shorts with only 7% false alarms and considerably reduced computational time.

Eh?Legalizer: A High Performance Standard-Cell Legalizer Observing Technology Constraints

The legalization step is performed after global placement where wire length and routability are optimized or during timing optimization where buffer insertion or gate sizing are applied to meet timing requirements. Therefore, an ideal legalization approach must preserve the quality of the input placement in terms of routability, wire length, and timing constraints. These requirements indirectly impose maximum and average cell movement constraints during legalization. In addition, the legalization step should effectively manage white space availability with a highly efficient runtime in order to be used in an iterative process such as timing optimization. In this article, a robust and fast legalization method called Eh?Legalizer for standard-cell placement is presented. Eh?Legalizer legalizes input placements while minimizing the maximum and average cell movements using a highly efficient novel network flow-based approach. In contrast to the traditional network flow-based legalizers, areas with high cell utilizations are effectively legalized by finding several candidate paths and there is no need for a post-process step. The experimental results conducted on several benchmarks show that Eh?Legalizer results in 2.5 times and 3.3 times less the maximum and average cell movement, respectively, while its runtime is significantly (18×) lower compared to traditional legalizers. In addition, the experimental results illustrate the scalability and robustness of Eh?Legalizer with respect to the floorplan complexity. Finally, the detailed-routing results show detailed-routing violations are reduced on average by 23% when Eh?Legalizer is used to generate legal solutions.

The impact of industry-organized contests on EDA education

The Electronic Design Automation (EDA) community is faced with an exponential increase in the complexity of the problems that it has to solve. These problems challenge the EDA community to find innovative techniques for training the next generation of researchers. This work discuss how international contests in EDA can play a pivotal role in the education and industry practices. We discuss the impact of our these contests on bridging the gap between industry and academia, training of the graduate students and building collaborations between different researchers. We compare the impact of papers originated from the effort of team winners in such contests compared to the best papers in annual International Symposium on Physical Design (ISPD) conference and Design Automation Conference (DAC). Finally, we also discuss the impact of the contests on the industry organizers and how they benefit from them.