Nitz Saputra

A Fully-Integrated, Short-Range, Low Data Rate FM-UWB Transmitter in 90 nm CMOS

This paper presents a fully-integrated 3-5 GHz-band FM-UWB transmitter implemented in 90 nm bulk CMOS. The front-end consists of an RF current-controlled oscillator (RF-ICO) and class-AB power amplifier. Transmit data modulates a sub-carrier oscillator. The 2-FSK modulated output is amplified by a transconductor, and directly modulates the RF-ICO tune input. A successive approximation register (SAR) algorithm and on-chip all-digital frequency-locked loop (FLL) calibrate the carrier and sub-carrier frequencies. All voltage and current references required by the transmitter are included on-chip. The 0.2 × 0.5 mm2 active area transmitter consumes 900 μW from a 1 V supply. Energy efficiency of the transmitter is 9 nJ/bit running continuously at 100 kbits/s.

A Short-Range Low Data-Rate Regenerative FM-UWB Receiver

A regenerative frequency-modulated ultra-wideband (FM-UWB) receiver for low data rate (<; 100 kbits/s) and short-distance ( <;10 m) reception in the 4-5-GHz band, consisting of a 35-dB gain preamplifier, envelope detector/demodulator, IF amplifier, and 50-Ω test buffer is described. The tunable (3.8-5.1 GHz) receiver front-end operates on a 50-MHz sub-band that is selected, amplified, and transformed from FM to amplitude modulated by a regenerative preamplifier. Energy efficiency of the regenerative FM-UWB receiver compared to previously published FM-UWB implementations is improved by a factor of 8, to 22 nJ/bit. Measured receiver sensitivity is -84 dBm at 100-kbits/s data rate (10-3 bit-error rate). Implemented in 65-nm bulk CMOS, the 0.3 mm2 test chip consumes 2.2 mW (excluding test buffer) from a 1-V supply.

An Assessment of µ-Czochralski, Single-Grain Silicon Thin-Film Transistor Technology for Large-Area, Sensor and 3-D Electronic Integration

Single-grain (SG) thin-film transistors (TFTs) fabricated inside location-controlled silicon grains using the mu-Czochralski method are benchmarked for analog and RF applications. Each silicon grain is defined by excimer laser recrystallization of polysilicon. Thin-film transistors may be fabricated in this manner on silicon or low-cost flexible plastic substrates as processing temperatures remain below 350degC, making the SG-TFT a potential enabling technology for large-area highly integrated electronic systems or systems-in-package with low manufacturing cost. Operational amplifier and voltage reference circuits of varying complexity were designed and measured in order to evaluate the effects of channel position and processing variation on analog circuits. A two-stage telescopic cascode operational amplifier fabricated in an experimental 1.5 mum SG-TFT technology demonstrates a DC gain of 55 dB (unity-gain bandwidth of 6.3 MHz), while a prototype CMOS voltage reference with a power supply rejection ratio (PSRR) of 50 dB is also demonstrated. With fT comparable to single-crystal MOSFETs of comparable gate length, the SG-TFT can also enable RF circuits for wireless applications. A 12 dB gain RF cascode amplifier with on-chip inductors and operating in the 433 MHz ISM band is demonstrated. Excellent agreement with simulations is attained using a modified BSIM-SOI model extracted from measurements of experimental SG-TFT devices.

A Fully Integrated Wideband FM Transceiver for Low Data Rate Autonomous Systems

A frequency-agile FM-UWB transceiver (Tx/Rx) with full on-chip calibration aimed at low data rate autonomous wireless sensing applications is described. The subcarrier VCO, 3-phase CCO, and frequency-tripling PA in the transmit path produce a wideband, double-FM output at -10.1 dBm-pk (FCC compliant). A tunable LNA, envelope detector, limiter, and FSK demodulator comprise the receiver. Digitally programmable matching networks at the PA output and LNA input facilitate independent tuning of Tx and Rx across the 3-5 GHz band. An on-chip SAR-FLL controlling 5 DACs (3 I-DACs and 2 C-DACs) performs a full Tx/Rx calibration in less than 2 ms. Designed for continuous operation at 100 kb/s, measured Rx sensitivity is -80.5 dBm (10 -3 BER), and average Tx/Rx energy efficiency is 6 nJ/bit. Total dissipation for the 0.9 mm 2 IC implemented in 90 nm RF-CMOS is 630 μW in Tx and 580 μW in Rx mode from a 1 V supply.

A 900μW, 3–5GHz integrated FM-UWB transmitter in 90nm CMOS

A fully-integrated 3–5GHz-band FM-UWB transmitter implemented in 90nm bulk CMOS is described. The transmitter includes: a sub-carrier oscillator, a voltage reference, a transconductance amplifier, a RF current-controlled oscillator and a power amplifier. Self-calibration circuitry based on all-digital frequency-locked loop (FLL) using a successive approximation register (SAR) algorithm is included on-chip. The 0.2×0.5mm2 active area transmitter consumes 900μ\Υ from a IV supply. Energy consumption is 9nJ/bit at continuous data rate of 100kbit/s.

A low-power digitally controlled wideband FM transceiver

A frequency-agile, low-power 3-5 GHz FM transceiver with on-chip calibration, and digital control of Rx gain, Tx power, and carrier frequency is described. The FCC-compliant transmitter incorporates a 3-phase CCO and frequency-tripling PA. A tunable LNA, envelope detector, limiter, and FSK demodulator comprise the receiver. Measured Rx sensitivity is -80.5 dBm (10-3 BER) at 100 kb/s. The 0.9 mm2 IC fabricated in 90 nm RF-CMOS dissipates 630 μW in Tx and 580 μW in Rx mode from a 1 V supply.

A 2.2 mW regenerative FM-UWB receiver in 65 nm CMOS

A 4–4.5 GHz receiver front-end consisting of a 35 dB voltage gain regenerative amplifier, ultra-narrowband RF filter and an envelope detector demodulator for FM-UWB communication is described in this paper. Implemented in 65 nm CMOS, the measured receiver sensitivity is −83 dBm at 100 kbps data rate with 15 dB output SNR (10−6 BER). The 0.3 mm2 test chip includes a 50 Ohm buffer amplifier to facilitate testing and consumes 2.2 mW (excluding buffer) from a 1 V supply.

Sigma delta ADC with a dynamic reference for accurate temperature and voltage sensing

A second-order sigma-delta analog-to-digital converter (ADC) with 12-bit absolute accuracy has been designed using a 0.7 mum CMOS technology. The ADC is part of a temperature sensor, and they both share a dynamic band-gap reference voltage, which is trimmed at room temperature. By using precision techniques such as chopping, correlated double-sampling and dynamic element matching, this reference voltage has a temperature coefficient of 3.5 ppm/degC over the range -40degC to 125degC. Its curvature error is corrected at the system level by means of a look-up-table-driven feedback loop. The result is an accurate temperature sensor with, in addition, accurate voltage sensing capability. The ADCs input dynamic range extends from 0 to VDD, for VDD ranging from 2.5 V to 5.5 V. The chip has an active area of 4.9 mm2, and a current consumption of 85 muA.

Single-grain Si thin-film transistors for analog and RF circuit applications

Single-grain (SG) Si-TFTs fabricated inside a location-controlled grain have SOI-like performance. To validate their potential for circuit application, key analog and RF building blocks are characterized. An operational amplifier (Opamp) and a voltage reference (Vref) demonstrate DC gain of 50 dB and power supply rejection ratio (PSRR) of 50 dB, respectively. With fT in the GHz range, SG-TFTs enable RF circuit design below 1 GHz. An RF cascode amplifier circuit is demonstrated.

Single Grain Si TFTs for RF and 3D ICs

Single-grain Si TFTs have been fabricated using accurate 2D location control of large Si grain with the ?-Czochralski process. TFTs fabricated inside the crystalline islands of 6 ?m show a mobility (600cm2/Vs) as high as that of the SOI counterpart, despite of the low-temperature (<350oC) process. By applying a tensile stress into the grain, the mobility surpass even the SOI counterparts. We have succeeded in controlling crystallographic orientation of the location-controlled Si grains as well, by combination of metal induced lateral crystallization and the micro-Czochralski process. Owing to the orientation control, uniformity in device properties approaches to the level of the SOI counterpart. Using the high performance single-grain (SG) Si TFTs, we have fabricated RF amplifier. The cut-off frequency of the RF device is 5.5 GHz with a channel length of 1.5 ?m. We have even succeeded to stack two SG-TFT layers with which CMOS inverters were fabricated. This will open several new applications in TFTs of RF wireless communication, 3D-ICs with device level integration, and flexible electronics.