Alessandro Baiano

An Assessment of µ-Czochralski, Single-Grain Silicon Thin-Film Transistor Technology for Large-Area, Sensor and 3-D Electronic Integration

Single-grain (SG) thin-film transistors (TFTs) fabricated inside location-controlled silicon grains using the mu-Czochralski method are benchmarked for analog and RF applications. Each silicon grain is defined by excimer laser recrystallization of polysilicon. Thin-film transistors may be fabricated in this manner on silicon or low-cost flexible plastic substrates as processing temperatures remain below 350degC, making the SG-TFT a potential enabling technology for large-area highly integrated electronic systems or systems-in-package with low manufacturing cost. Operational amplifier and voltage reference circuits of varying complexity were designed and measured in order to evaluate the effects of channel position and processing variation on analog circuits. A two-stage telescopic cascode operational amplifier fabricated in an experimental 1.5 mum SG-TFT technology demonstrates a DC gain of 55 dB (unity-gain bandwidth of 6.3 MHz), while a prototype CMOS voltage reference with a power supply rejection ratio (PSRR) of 50 dB is also demonstrated. With fT comparable to single-crystal MOSFETs of comparable gate length, the SG-TFT can also enable RF circuits for wireless applications. A 12 dB gain RF cascode amplifier with on-chip inductors and operating in the 433 MHz ISM band is demonstrated. Excellent agreement with simulations is attained using a modified BSIM-SOI model extracted from measurements of experimental SG-TFT devices.

Stacking of Single-Grain Thin-Film Transistors

Vertical stacking of transistors is a promising technology which can realize compact and high-speed integrated circuits (ICs) with a short interconnect delay and increased functionality. Two layers of low-temperature fabricated single-grain thin-film transistors (SG TFTs) have been monolithically integrated. Using a finite element method (FEM) simulation, the damage to the bottom layer devices during laser crystallization of the top layer silicon layer has been investigated. N-channel metal–oxide–semiconductor (n-MOS) mobilities are 565 and 393 cm2 V-1 s-1 and p-channel MOS (p-MOS) mobilities are 159 and 141 cm2 V-1 s-1, for the top and bottom layers respectively. A three-dimensional (3D) complementary MOS (CMOS) inverter has also been fabricated, with one transistor on the bottom layer and the other on the top layer.

Strained Single-Grain Silicon n- and p-Channel Thin-Film Transistors by Excimer Laser

We have investigated the carrier mobility enhancement of the n- and p-channel single-grain silicon thin-film transistors by the ¿-Czochralski process at a low-temperature process (< 350°C). The high laser energy density near the ablation phenomenon that completely melts the grain filter during the crystallization is responsible for the high tensile strain of the silicon grains, which leads to carrier mobility enhancement.

Single-grain Si thin-film transistors for analog and RF circuit applications

Single-grain (SG) Si-TFTs fabricated inside a location-controlled grain have SOI-like performance. To validate their potential for circuit application, key analog and RF building blocks are characterized. An operational amplifier (Opamp) and a voltage reference (Vref) demonstrate DC gain of 50 dB and power supply rejection ratio (PSRR) of 50 dB, respectively. With fT in the GHz range, SG-TFTs enable RF circuit design below 1 GHz. An RF cascode amplifier circuit is demonstrated.

Single Grain Si TFTs for RF and 3D ICs

Single-grain Si TFTs have been fabricated using accurate 2D location control of large Si grain with the ?-Czochralski process. TFTs fabricated inside the crystalline islands of 6 ?m show a mobility (600cm2/Vs) as high as that of the SOI counterpart, despite of the low-temperature (<350oC) process. By applying a tensile stress into the grain, the mobility surpass even the SOI counterparts. We have succeeded in controlling crystallographic orientation of the location-controlled Si grains as well, by combination of metal induced lateral crystallization and the micro-Czochralski process. Owing to the orientation control, uniformity in device properties approaches to the level of the SOI counterpart. Using the high performance single-grain (SG) Si TFTs, we have fabricated RF amplifier. The cut-off frequency of the RF device is 5.5 GHz with a channel length of 1.5 ?m. We have even succeeded to stack two SG-TFT layers with which CMOS inverters were fabricated. This will open several new applications in TFTs of RF wireless communication, 3D-ICs with device level integration, and flexible electronics.

Single-Grain Germanium TFTs

We review our recent achievements in location-control of Ge grains and high performance single-grain (SG) Ge thin film transistor (TFT) fabricated inside a Ge grain. Large Ge grains having a grain size of 10 µm were obtained at predetermined positions by the µ-Czochralski process using excimer-laser and sputtered a-Ge layer. TFTs were fabricated inside the single grain of Ge. Capping silicon dioxide was applied before the laser crystallization with which a high quality Ge/insulator interface was formed during the laser annealing. Source/drain regions were formed by doped Si instead of the Ge, which ensures a low contact resistance and suppresses fast dopant diffusion in the channel. N- and p-channel SG Ge TFTs showed electron and hole mobility of as high as 3337cm^2/Vs and 1719cm^2/Vs, respectively. On/off current ratio for the both types of TFTs was in the order of 10^7.

High Performance n- and p-channel Strained Single Grain Silicon TFTs using Excimer Laser

In this paper we investigate the carriers mobility enhancement of the n- and p-channel single-grain silicon thin-film transistors (SG-TFTs) by μ-Czochralski process at low-temperature process (