Tatsuya Kamimura

A ring-VCO-based injection-locked frequency multiplier using a new pulse generation technique in 65 nm CMOS

This paper proposes a low-phase-noise ring-VCO-based frequency multiplier with a new subharmonic direct injection locking technique that only uses a time-delay cell and four MOS transistors. Since the proposed technique behaves as an exclusive OR and can double the reference signal frequency, it increases phase correction points and achieves low phase noise characteristic across the wide output frequency range. The frequency multiplier was fabricated by using 65 nm Si CMOS process. Measured 1-MHz-offset phase noise at 6.34 GHz with reference signals of 528 MHz was −113dBc/Hz.

A sub-1mw 5.5-GHz PLL with digitally-calibrated ILFD and linearized varactor for low supply voltage operation

This paper proposes an ultra-low-power 5.5GHz PLL which employs a divide-by-4 injection-locked frequency divider (ILFD) and linearity-compensated varactor for low supply voltage operation. The digital calibration circuit is introduced to control the ILFD frequency automatically. The proposed varactor, which applies a forward-body-bias (FBB) technique, is employed for linear-frequency-tuning under the power supply of 0.5 V. The proposed PLL was fabricated in 65 nm CMOS. With a 34.3-MHz reference, it shows a 1-MHz-offset phase noise of -106 dBc/Hz, a reference spur level lower than -65 dBc, and the total power consumption of 950μW at 5.5 GHz.

A 0.5-V 5.5-GHz class-C-VCO-based PLL with ultra-low-power ILFO in 65 nm CMOS

In this paper, an ultra-low-power 5.5-GHz PLL is proposed which employs the new divide-by-4 injection-locked frequency divider (ILFD) and a class-C VCO for operation under a power supply of 0.5 V. A forward-body-biasing (FBB) technique can decrease threshold voltage of MOS transistors, which can improve operation frequency and can widen the lock range of the ILFD. The double-switch injection technique is also proposed to widen the lock range of the ILFD. The proposed PLL was fabricated in 65nm CMOS. The whole circuit consumes 1.6 mW under the power supply of 0.5V. With a 34.6-MHz reference, it shows a 1-MHz-offset phase noise of -105 dBc/Hz and a reference spur level lower than -65dBc at 5.5 GHz.

A Multi-Band Quadrature Clock Generator With High-Pass-Filtered Pulse Injection Technique

A high-pass-filtered (HPF) pulse injection technique is proposed to reduce spurs near the carrier signal due to injection locking. By using this technique, a multi-band quadrature clock generator consisting of a wide-frequency range injection-locked PLL and a frequency-selectable local buffer is demonstrated. The proposed clock generator was fabricated in a 65 nm CMOS. For a 100 MHz reference, the circuit can output 1.0, 2.0, and 4.0 GHz quadrature outputs with an eight-phase VCO and the buffer. It shows an 1 MHz-offset phase noise -105 dBc/Hz and a reference spur level of -50 dBc at 2.0 GHz, with enabling HPF pulse injection. The total power consumption is lower than 32 mW at 4 GHz.

Fractionally Injection-Locked Frequency Multiplication Technique with Multi-Phase Ring Voltage-Controlled Oscillator

In this paper, we present a fractionally injection-locked frequency multiplication technique that can solve the tradeoff between the selectable frequency step and phase noise of injection-locked frequency multipliers (ILFMs). For a given output frequency step, the phase noise of the proposed ILFM is lower than that of conventional ILFMs because higher-frequency signals can be injected. The proposed ILFM was fabricated using a 180 nm Si complementary metal oxide semiconductor (CMOS) process. 1/2-, 1/3-, 1/4-, and 1/6-integral frequency multiplications were realized, which means that the output frequency resolution is 6 times as high as that of conventional ILFM. When the reference frequency was 100 MHz, the measured phase noise at 725 (= 100×29/4) MHz was -120 dBc/Hz at a 1 MHz offset, and that at 767 (= 100×23/3) MHz was -119 dBc/Hz at 1 MHz offset.

A 950μW 5.5-GHz low voltage PLL with digitally-calibrated ILFD and linearized varactor

This paper proposes an ultra-low-power 5.5-GHz PLL which employs a divide-by-4 injection-locked frequency divider (ILFD), which is calibrated by digital circuits, and linearity-compensated varactors for low supply-voltage operation. The proposed PLL was fabricated in 65nm CMOS. It shows a 1-MHz-offset phase noise of -106 dBc/Hz and the total power consumption of 950μW at 5.5 GHz.

0.1 V 13 GHz Transformer-Based Quadrature Voltage-Controlled Oscillator with a Capacitor Coupling Technique in 90 nm Complementary Metal Oxide Semiconductor

A low power-supply voltage and high-frequency quadrature voltage-controlled oscillator (QVCO) using a combination of capacitor coupling and transformer feedback techniques is presented. The capacitor coupling technique can boost the transconductance of the LC-VCO core and coupling transconductance of QVCO at high frequency. Also, this technique can improve the quality factor of the QVCO at high frequency with low power-supply voltage, compared with the conventional QVCO. In addition, the capacitor coupling QVCO with transformer feedback can improve the quality factor of QVCO. Using this topology, the QVCO is able to operate at over 10 GHz with lower power-supply voltage. Implemented in the 90 nm complementary metal oxide semiconductor (CMOS) process, the proposed QVCO measures 1-MHz-offset phase noise of -94 dBc/Hz at 13 GHz while consuming 0.68 mW from a 0.1 V power-supply.