Nobuhiko Sato

Epitaxial layer transfer by bond and etch back of porous Si

We demonstrate a novel method for bond and etch back silicon on insulator in which an epitaxial Si layer over porous Si is transferred onto a dissimilar substrate by bonding and etch back of porous Si. The highest etching selectivity (100 000:1) between the porous Si and the epitaxial layer is achieved by the alkali free solution of HF, H2O2, and H2O which is essential for this single etch‐stop method to produce a submicron‐thick active layer with superior thickness uniformity (473±14 nm) across a 5 in. silicon‐on‐insulator wafer.

Epitaxial growth on porous Si for a new bond and etchback silicon-on-insulator

A new bond and etchback silicon-on-insulator (SOI) has been proposed and demonstrated, in which epitaxial layers on porous Si are transferred by bonding and etching back porous Si. The key processes are epitaxial growth on porous Si and selective removal of porous Si. In the epitaxial layers over porous Si, the major defects are stacking faults, which can be reduced to 10 3 to 10 4 /cm 2 by raising the H 2 prebake temperature and lengthening the immersion time in diluted HF prior to the prebake. Bondable smooth surfaces were formed at growth temperatures below 900°C. A highly selective etchant of HF-H 2 O 2 was discovered and enabled us to etch off porous Si with a selectivity of 10 5 , leaving behind epitaxial layers on the oxidized handle wafers. The rough as-etched SOI surface was smooth comparable to that of the commercially available bulk-polished wafer, and boron concentration in the SOI-Si layer was simultaneously decreased to ∼1 x 10 16 /cm 3 , by H 2 annealing. Finally, a uniform SOI layer of 507 nm ±3% across a 5 in. wafer was achieved by this method.

Hydrogen annealed silicon‐on‐insulator

Hydrogen annealing effects on silicon‐on‐insulator (SOI) materials are reported. High boron concentration of ∼2×1018/cm3 in 0.1‐μm‐thick SOI layer produced by bond and etch‐back SOI (BESOI) method is reduced to ∼ 5×1015/cm3 by annealing at 1150 °C for 1 h. The BESOI surface became very smooth comparable to commercially available polished wafer simultaneously. Separation‐by‐implantation‐of‐oxygen wafer was also smoothed by the hydrogen anneal. This is due to surface migration of Si atoms driven by surface energy minimization after removing native oxide.

Advanced Quality in Epitaxial Layer Transfer by Bond and Etch-back of Porous Si.

We report recent qualitative advances in bonding and etch-back of silicon on insulator (SOI) using structure-sensitive selective etching of porous Si. The defect density in the epitaxial layer grown on the porous Si is lowered to 3.5 x 10 2 /cm 2 by raising the H 2 prebake temperature in conjunction with the preinjection technique in which a small amount of Si is supplied during the high-temperature H 2 prebake prior to epitaxial growth. H 2 annealing also gives a smooth SOI surface comparable to the bulk polished wafer. Improved thickness uniformity of ±1.8% is achieved using the single wafer processing epi-reactor. The electrical characteristics are evaluated by fabricating pn-junction diode.

Extremely High Selective Etching of Porous Si for Single Etch-Stop Bond-and-Etch-Back Silicon-on-Insulator

The etching characteristics of porous Si in comparison with bulk Si have been investigated for the ultra thin film (UTF) single etch-stop bond-and-etch-back silicon-on-insulator (BESOI). It is found out that porous Si can be selectively etched exclusively by a mixture of HF, H2O2 and H2O due to the structure-sensitive mechanism, that is, inner reaction by capillary-induced penetration of the etchant into the pores followed by collapsing the Si columns. This extremely high etching selectivity reaches as large as 105, which results in excellent SOI layer thickness variation of less than 7% across 5-inch SOI wafers with sub-µ m and sub-100-nm thicknesses.

Growth and characterization of GaAs epitaxial layers on Si/porous Si/Si substrate by chemical beam epitaxy

The initial growth of GaAs films on a Si/porous Si/Si (SPS) substrate has been investigated using reflection high-energy electron diffraction. The morphology and the thickness have been examined by a Nomarski optical microscope and scanning electron microscope, respectively. The results of the low temperature photoluminescence studies have shown that a significant reduction in the residual thermal tensile stress can be achieved with reduced growth temperature. The 77 K photoluminescence spectra for GaAs/Si show a strain-induced splitting between the heavy and light hole valence bands which corresponds to a biaxial tensile stress of 2.45 kbar acting on the GaAs layer where the same for GaAs/SPS grown at 450 °C is 1.69 kbar. The results have shown that a SPS substrate with the combination of low temperature growth is a promising candidate for obtaining GaAs films with low stress.

Suppression of Si etching during hydrogen annealing of silicon-on-insulator

Generally, polishing is employed as the final treatment of silicon-on-insulator (SOI) at the expense of SOI thickness reduction, because surface microroughness affects the gate oxide integrity. Hydrogen annealing of SOI wafers (Sato and Yonehara, 1994) was originated to replace the polishing, and was traced by several groups. This novel method is advantageous in that there is no thickness reduction in principle. However, in view of the Si etching during hydrogen annealing, various etching rates have been reported in the literature, leading to the question of how much Si is consumed or how much SOI thickness reduction is suppressed. In this paper, Si etching during hydrogen annealing is investigated by using ELTRAN wafers, which are fabricated by transferring epitaxial layers on porous Si on to handle wafers. The lowest reported etching rate to date is achieved.

Thermal Stress Relaxation in GaAs Layer on New Thin Si Layer over Porous Si Substrate Grown by Metalorganic Chemical Vapor Deposition

We have proposed and introduced a thin Si layer over porous Si (SPS) substrate instead of the conventionally used Si substrate to overcome the residual thermal stress in GaAs layer on Si substrate (GaAs/Si). From the results of X-ray diffraction, low-temperature photoluminescence and Raman scattering, it was found that a significant reduction of the residual thermal tensile stress has been achieved. Our data clearly show that the SPS substrate is a promising substrate for overcoming the problems in GaAs/Si.

Practical High-Resistivity Silicon-on-Insulator Solution for Spiral Inductors in Radio-Frequency Integrated Circuits

The effect of high-resistivity (high-R) silicon-on-insulator (SOI) substrates on spiral inductors in radio-frequency integrated circuits (RF ICs) has been investigated by experiment and simulation. The effect of the high-R substrates on the spiral inductors saturates at a resistivity above 2–3 kΩ cm, and the resistivity must be maintained high with a thickness of about 300 µm. The resistivity dependence of the high-R effect can be explained with a dielectric loss mechanism in silicon substrates. The thickness criterion of the effect can be explained with an inductor model that includes magnetically induced current in a ground plane. On the basis of experimental results and discussion, we conclude that a commercially available high-R wafer with carefully designed back-end process is sufficient for obtaining the maximum effect of high-R substrates.

Selective nucleation based epitaxy (sentaxy): Investigation of initial nucleation stages

Abstract A dynamic process of nucleation and growth of CVD-Si over amorphous SiO x ( x Sentaxy where only one nucleus grows on an artificial nucleation site.