Masataka Ito

Suppression of Si etching during hydrogen annealing of silicon-on-insulator

Generally, polishing is employed as the final treatment of silicon-on-insulator (SOI) at the expense of SOI thickness reduction, because surface microroughness affects the gate oxide integrity. Hydrogen annealing of SOI wafers (Sato and Yonehara, 1994) was originated to replace the polishing, and was traced by several groups. This novel method is advantageous in that there is no thickness reduction in principle. However, in view of the Si etching during hydrogen annealing, various etching rates have been reported in the literature, leading to the question of how much Si is consumed or how much SOI thickness reduction is suppressed. In this paper, Si etching during hydrogen annealing is investigated by using ELTRAN wafers, which are fabricated by transferring epitaxial layers on porous Si on to handle wafers. The lowest reported etching rate to date is achieved.

Reduction of crystalline defects to 50/cm/sup 2/ in epitaxial layers over porous silicon for ELTRAN/sup R/ process

As the design rules of large scale integrated circuits (LSIs) progress, excellent gate oxide integrity (GOI) is demanded despite the requirement for thinner gate oxides. Crystal originated particles (COPs) are currently reported as killer defects for GOI on Czochralski-silicon (CZ-Si) wafers; however, an epitaxial layer on the CZ substrate gives quite good GOI characteristics because of the significantly small amount of COPs in it. It is expected that the epitaxial layer would be used in silicon-on-insulator (SOI), which is one of the candidates for high speed and low power consumption LSIs. We have already reported the epitaxial layer transfer (ELTRAN) method (Yonehara et al, 1994, and Sato et al, 1995), in which the epitaxial layer on porous Si was transferred on to a handle wafer to form an SOI wafer by bonding and etching back of porous Si with extremely high etching selectivity. In this paper, it is reported that the density of stacking faults, which is the major defect in these wafers, is significantly reduced to 50/cm/sup 2/ by controlling both the porous structure and the prebaking step before growth.

Scalability potential in ELTRAN/sup (R)/ SOI-epi wafer

For coming device applications, advanced requirements for silicon-on-insulator (SOI) wafers are increasing. One of the most important items is scalability that includes scaling up of the wafer diameter and scaling down of the SOI layer thickness (t/sub SOI/). 300 mm wafers and ultra thin SOI with t/sub SOI/ less than 100 nm will be required according to the ITRS (SIA, 1999). 300 mm SOI wafers are essential for process cost reduction of the most advanced device applications with shrunken design rules. On the other hand, ultra thin SOI layers are important especially for fully depleted SOI-MOSFETs. In this paper, we applied ELTRAN/sup (R)/ technology (Yonehara et al., 1994) to 300 mm SOI and ultra thin SOI in order to demonstrate the scalability.

Gettering Control at Bonding Interface in ELTRAN

ABSTRUCT: Heavy metal gettering capability on ELTRAN® was studied by controlling surface treatments for handle wafer prior to wafer bonding. Hydrophobic bonding pre-treatments wafer had much higher heavy metal gettering capability at bonding interface than hydrophilic wafer. In the case of hydrophilic bonding pre-treatments, atomically flat bonding interface was observed by cross-sectional TEM. On the other hand, in the case of hydrophobic bonding pre-treatments, “nano gaps” were observed at bonding interface. We concluded that these differences in the structure at the bonding interface caused the difference in the gettering capability. It is possible to control gettering capability by no additional steps in SOI wafer process.