Kiyofumi Sakaguchi

Epitaxial layer transfer by bond and etch back of porous Si

We demonstrate a novel method for bond and etch back silicon on insulator in which an epitaxial Si layer over porous Si is transferred onto a dissimilar substrate by bonding and etch back of porous Si. The highest etching selectivity (100 000:1) between the porous Si and the epitaxial layer is achieved by the alkali free solution of HF, H2O2, and H2O which is essential for this single etch‐stop method to produce a submicron‐thick active layer with superior thickness uniformity (473±14 nm) across a 5 in. silicon‐on‐insulator wafer.

Epitaxial growth on porous Si for a new bond and etchback silicon-on-insulator

A new bond and etchback silicon-on-insulator (SOI) has been proposed and demonstrated, in which epitaxial layers on porous Si are transferred by bonding and etching back porous Si. The key processes are epitaxial growth on porous Si and selective removal of porous Si. In the epitaxial layers over porous Si, the major defects are stacking faults, which can be reduced to 10 3 to 10 4 /cm 2 by raising the H 2 prebake temperature and lengthening the immersion time in diluted HF prior to the prebake. Bondable smooth surfaces were formed at growth temperatures below 900°C. A highly selective etchant of HF-H 2 O 2 was discovered and enabled us to etch off porous Si with a selectivity of 10 5 , leaving behind epitaxial layers on the oxidized handle wafers. The rough as-etched SOI surface was smooth comparable to that of the commercially available bulk-polished wafer, and boron concentration in the SOI-Si layer was simultaneously decreased to ∼1 x 10 16 /cm 3 , by H 2 annealing. Finally, a uniform SOI layer of 507 nm ±3% across a 5 in. wafer was achieved by this method.

Advanced Quality in Epitaxial Layer Transfer by Bond and Etch-back of Porous Si.

We report recent qualitative advances in bonding and etch-back of silicon on insulator (SOI) using structure-sensitive selective etching of porous Si. The defect density in the epitaxial layer grown on the porous Si is lowered to 3.5 x 10 2 /cm 2 by raising the H 2 prebake temperature in conjunction with the preinjection technique in which a small amount of Si is supplied during the high-temperature H 2 prebake prior to epitaxial growth. H 2 annealing also gives a smooth SOI surface comparable to the bulk polished wafer. Improved thickness uniformity of ±1.8% is achieved using the single wafer processing epi-reactor. The electrical characteristics are evaluated by fabricating pn-junction diode.

Extremely High Selective Etching of Porous Si for Single Etch-Stop Bond-and-Etch-Back Silicon-on-Insulator

The etching characteristics of porous Si in comparison with bulk Si have been investigated for the ultra thin film (UTF) single etch-stop bond-and-etch-back silicon-on-insulator (BESOI). It is found out that porous Si can be selectively etched exclusively by a mixture of HF, H2O2 and H2O due to the structure-sensitive mechanism, that is, inner reaction by capillary-induced penetration of the etchant into the pores followed by collapsing the Si columns. This extremely high etching selectivity reaches as large as 105, which results in excellent SOI layer thickness variation of less than 7% across 5-inch SOI wafers with sub-µ m and sub-100-nm thicknesses.

ELTRAN/sup (R)/ by water-jet splitting in stress-controlled porous Si

The ELTRAN/sup (R)/ SOI wafer process (Yonehara et al, 1994) has effectively used porous Si in the epitaxial and etching processes. In addition, porous Si again plays the other significant role in cost reduction. If the bonded pairs are split at the porous Si layers and the wasted starting materials (device wafers) are reused for the next device wafers, the manufacturing cost can be dramatically reduced. The splitting technique was developed and demonstrated using double layered porous Si in conjunction with water jets. The mechanism of splitting was investigated from the viewpoint of the stress in porous Si. The dynamic stress configuration was observed and controlled for the splitting of double porous Si layers. By reusing the device wafers, three-cycled ELTRAN/sup (R)/ wafers were successfully fabricated from one device wafer. SOI quality was found not to be degraded by the device wafer reuse and to be comparable to that of the conventional process.

High-quality epitaxial layer transfer (ELTRAN) by bond and etch-back of porous Si

The small thickness variation and the high crystalline quality in the SOI films are required for the large scale integration of devices. BESOI is one of the attractive methods due to its layer thickness versatility and productivity particularly in large-scale wafers. Recently, we have reported a novel BESOI method, in which an epitaxial layer on porous Si is transferred onto another handle wafer by bonding and etching back of porous Si (ELTRAN). The structure difference and the abrupt interface between porous and bulk Si gives the very high etching selectivity (10/sup 4/-10/sup 5/), so that it can replace the dopant-sensitive selective etching in the existing BESOI, and allow high-temperature heat treatments (/spl ges/1100/spl deg/C) both to grow the good epitaxial layer and to increase the bonding strength. In this paper, the high etching selectivity and the resultant SOI thickness uniformity are discussed. The crystalline quality of the SOI layer is evaluated by defect delineate etching and p-n junction diodes.