Nobukazu Teranishi

No image lag photodiode structure in the interline CCD image sensor

An undesirable image lag with a long time constant was found in the interline CCD image sensor having N+P-junction photodiode (PD). This paper clarifies the image lag mechanism and proposes a new photodiode structure having no image lag. The image lag measurement method and the experimental results are also given. The experimental results quantitatively agreed with the analytical model, in which signal electrons are assumed to be transferred from the PD to the vertical CCD as a small subthreshold current. To eliminate the image lag, a P+NP-structure PD with low donor concentration was proposed, where all the signal electrons can be quickly transferred before the subthreshold condition begins. As a result, the decay lag values of the 1st and the 2nd fields were reduced to half and the decay lags after the 3rd field were not observed.

Required Conditions for Photon-Counting Image Sensors

The required conditions of photon counting and single-photon detection are theoretically derived for four different approaches: 1) photon counting and single-shot imaging; 2) photon counting and multiple-shot imaging; 3) single-photon detection and single-shot imaging; and 4) single-photon detection and multiple-shot imaging. The most important parameter for all approaches is effective quantum efficiency (EQE), which is defined as QE multiplied by the temporal aperture ratio. To realize photon counting and single-shot imaging, EQE should be ~1. Even if EQE = 0.95, it cannot be realized with a 90% confidence level, whereas single-photon detection and single-shot imaging can be realized. When objects are stationary scenes or repeated phenomena, multiple-shot imaging is effective. The signal-to-noise ratio for multiple-shot imaging is increased with the square root of the shot number. The input-referred noise in the number of detected photoelectrons is expected to be less than 0.3e to realize electron counting, which is required for photon counting and single-photon detection. single-photon avalanche photodiodes and electron multiplication CCDs have achieved it, and “normal” image sensors, which do not use avalanche multiplication, can also realize it.

Technologies to improve photo-sensitivity and reduce VOD shutter voltage for CCD image sensors

New technologies to increase the photo-sensitivity and reduce the shutter voltage of the vertical over-flow-drain (VOD) have been developed for CCD image sensors. The photo-sensitivity was increased 40% by forming an anti-reflection film over the photodiode and reducing the thickness of the p/sup +/-layer formed at the photodiode surface. The VOD shutter voltage was reduced from 31 to 18 V by using an epitaxially grown substrate with double impurity concentration layers.

CCD image sensor for single sensor color camera

A 384(H) × 490(V) element interline CCD image sensor, using PN+ junction photodiodes without overlayer electrodes, a low-noise charge detector and CCD registers with large charge-handling capability, will be discussed. SNR is 71dB at device saturation light level of 1.51ux.

A 10 ps Time-Resolution CMOS Image Sensor With Two-Tap True-CDS Lock-In Pixels for Fluorescence Lifetime Imaging

A CMOS lock-in pixel image sensor with embedded storage diodes and lateral electric field modulation (LEFM) of photo-generated charge is developed for fluorescence lifetime imaging. The time-resolved CMOS image sensor (CIS) with twotap lock-in pixels achieves a very high time resolution of 10 ps when images are averaged over 30 frames, a very short intrinsic response time of 180 ps at 374 nm, and a low temporal random noise of 1.75e-rms with true correlated double sampling (CDS) operation. In addition, by using the LEFM and optimized process, a very high extinction ratio of approximately 94% at 472 nm laser diode is achieved. The usefulness of the proposed CIS is demonstrated for fluorescence lifetime imaging with the simulation and measurement results.

Evolution of optical structure in image sensors

On-chip optics in image sensors has played an important role for image sensor pixel shrinkage and image sensor progression on the whole. There are three key functions; light collecting, color filtering and new specific functions, all of which are reviewed with their future trends. For light collecting technologies, 1.12 um pixel FSI (front side illumination) with noble lightpipe, which is suitable for large chief ray angle lenses, is explained.

A Low Dark Leakage Current High-Sensitivity CMOS Image Sensor With STI-Less Shared Pixel Design

A CMOS image sensor with a low dark current and high sensitivity is developed with shallow trench isolation (STI) less shared pixel. By sharing in-pixel transistors, such as the reset transistor, select transistor, and source follower amplifier, each pixel achieves a high fill factor of 43% and a high sensitivity of 144.6 ke-/lx · s. In addition, compared with a conventional image sensor which has the STI structure in the pixel for isolation, the developed image sensor achieves a relatively low dark current of 104.5 e-/s/pixel (median), corresponding to a current density Jdark of approximately 30 pA/cm2 at 60 °C. This is a low value and the consequence of not using STI as pixel isolation. Both types of pixels, namely the conventional and the proposed active pixel sensor have the same pixel size of 7.5 × 7.5 μm2 and are fabricated by the same process. The developed imager with STI-less shared pixel obtains sufficiently good responses at 400 to 900 nm, and, particularly, a peak QE of 68% at 600 nm. This is suitable for scientific applications.

A 1/2-in 1.3 M-pixel progressive-scan IT-CCD for digital still camera applications

A 1/2-in 1.3 M-pixel progressive-scan interline-transfer charge-coupled-device (IT-CCD) image sensor has been developed for small, low-power mega-pixel digital still cameras (DSCs). The pixel size as small as 5 /spl mu/m square makes small-size progressive-scan IT-CCD (8.3/spl times/7.1 mm/sup 2/) for the SXGA format. A two-phase-drive horizontal-CCD with phosphorus-implanted storage regions helps reduce the driving voltage to 2.5 V, resulting in the power consumption of the device being as low as 146 mW. A new source-follower amplifier with separate p-well driver transistors achieves 12% higher gain than that obtained using a conventional amplifier. An overflow drain with a self-adjusting potential barrier can instantly remove superfluous charges in vertical-CCDs just before an exposure period, which enables DSCs to perform such functions as quick auto-focusing and dark-current removal. New dual operation modes for still and motion pictures can provide not only high-resolution color signals in a 15-frame/s 1050-line progressive mode but also wide-dynamic-range color signals in a 30-frame/s 525-line progressive mode. The latter mode employs a pixel-exchange-and-mix readout operation that helps halve the number of scanning lines with no loss in sensitivity and color information.

Driving voltage reduction in a two-phase CCD by suppression of potential pockets in inter-electrode gaps

This study reports an optimum design for a two-phase charge-coupled device (CCD) and limitations on its driving voltage reduction. The two-phase CCD to be used as a horizontal-CCD (H-CCD) in a CCD image sensor requires low-voltage and high-speed operation. Reducing the driving voltage, however, may induce potential pockets in the channel under the inter-electrode gaps which results in a fatal decrease in charge-transfer efficiency. In this case it is necessary to optimize the CCD design to be free of pocket generation. For this requirement, we conducted two-dimensional (2-D) device simulations for the two-phase CCD, whose potential barriers are formed by boron ion-implantation. Our simulations indicated that the edge position of the potential barrier region and the dose of boron-ion implantation would be important parameters for controlling the size of potential pockets. At an optimum edge position and a boron dose, the minimum driving voltage appears to be reducible to 1.1 V. Characteristics of potential pockets and methods of their suppression are also discussed.

An infrared-bi-color Schottky-barrier CCD image sensor for precise thermal images

An infrared-bi-color image sensor was developed with a barrier height controlled Schottky-barrier photo diode array for precise temperature images. Low and high barrier height diode pixels are arranged vertically next to one another using a selective area ion implantation technique. Conventional monochrome infrared image sensors frequently give wrong temperature images due to an unreasonable emissivity assumption. The infrared-bi-color image sensor can obtain the temperature image precisely with regard to the emissivity of the object.