Takeshi Inuo

A Gate-Level EHW Chip: Implementing GA Operations and Reconfigurable Hardware on a Single LSI

The advantage of Evolvable Hardware (EHW) over traditional hardware is its capacity for dynamic and autonomous adaptation, which is achieved through by Genetic Algorithms (GAs). In most EHW implementations, these GAs are executed by software on a personal computer (PC) or workstation (WS). However, as a wider variety of applications come to utilize EHW, this is not always practical. One solution is to have the GA operations carried out by the hardware itself, by integrating these together with reconfigurable hardware logic like PLA (Programmble Logic Array) or FPGA (Field Programmable Gate Array) on to a single LSI chip. A compact and quickly reconfigurable EHW chip like this could service as an off-the-shelf device for practical applications that require on-line hardware reconfiguration. In this paper, we describe an integrated EHW LSI chip that consists of GA hardware, reconfigurable hardware logic, a chromosome memory, a training data memory, and a 16-bit CPU core (NEC V30). An application of this chip is also described in a myoelectric artificial hand, which is operated by muscular control signals. Although, work on using neural networks for this is being carried out, this approach is not very promising due to the long learning period required for neural networks. A simulation is presented showing that not only is the EHW performance slightly better than with neural networks, but that the learning time is considerably reduced.

Techniques for Virtual Hardware on a Dynamically Reconfigurable Processor – An Approach to Tough Cases –

Virtual hardware is difficult to implement even on recent dynamically reconfigurable processors when the loop body of the target application cannot be stored in the set of quickly switch-able contexts. Here, techniques for such tough cases are proposed. Differential configuration which changes only different parts of similar contexts can drastically reduce the time for re-configuration. Pairwise context assignment policy can hide the overhead of configuration with double buffering. Out-of-order context switching enables execution of available context in advance. Through an implementation example on NEC’s DRP-1, it appears that the virtual hardware can be executed with practical speed by combining the proposed techniques.

Mapping algorithms for a multi-bit data path processing reconfigurable chip RHW

While FPGAs are mainly used for implementing general purpose logic circuits, the RHW works with the CPU to accelerate the computation intensive part of the application by reconfiguring its data paths and ALUs optimized for the algorithm. Hence the RRW was designed to implement multi-bit data paths and ALUs efficiently. We developed a new architecture that consists of a two-dimensional array of multi-bit original ALU that is composed of a type of adder with multi-functional pre-logics.

Arithmetic Operation Oriented Reconfigurable Chip: RHW

We have developed an ALU based reconfigurable device called RHW (Reconfigurable HardWare) that is designed to work with the CPU to accelerate the computation-intensive part of the application by reconfiguring its data paths and ALUs optimized for the algorithm. It is also important to develop high performance operation unit library to utilize function cells of RHW efficiently. This paper describes the basic architecture of the RHW, high performance operation unit library and evaluation results.