Nobuyasu Kanekawa

Fault detection and recovery coverage improvement by clock synchronized duplicated systems with optimal time diversity

Fast fault detection and recovery are indispensable to improve the availability of fail-safe and fault-tolerant systems. Fast fault detection and recovery can be realized by clock-synchronized duplicated systems with optimal time diversity, which have fast fault detection and recovery features. The experiments presented in this paper compare fault detection coverage and retry recovery coverage of a clock-synchronized system without optimal time diversity, a clock-synchronized system with optimal time diversity, and an I/O synchronized system. The experimental results show that clock-synchronized systems with optimal time diversity realize the highest fault detection and recovery coverage.

2.3 kVac 100 MHz multi-channel monolithic isolator IC

We have developed a multi-channel monolithic isolator IC that can provide 2.3 kVac isolation and 100 MHz signal transmission. This IC uses high voltage on-chip isolator technology using trench isolation with buried oxide on the SOI substrate and 0.4 /spl mu/m CMOS driver and receiver circuits. This technology enables to produce a 4-channel monolithic isolator with an area of 1.5 mm/sup 2/ and a consumption current of 0.5 mA per channel at a frequency of 50 MHz. We have also developed a one-chip modem interface IC that includes the multi-channel isolator and an analog front-end circuit.

Dependable onboard computer systems with a new method-stepwise negotiating voting

An algorithm for software voting, called stepwise negotiating voting, which can tolerate the faults in up to N-1 subsystems is introduced. The voter behaves as if it were a majority voter if the number of remaining subsystems is sufficient for majority voting, and standby redundancy is realized if the number of remaining subsystems becomes insufficient. With this voting method, the system can survive if more than one subsystem remains. The authors introduce a method for evaluating the dependability of systems. It is based on the viewpoint that not only the hardware reliability but also the reliability of data processing is important. It is assumed that only transient faults take place in the software behavior. The authors concept can be applied to computers in critical application fields, such as space development or engine control.<<ETX>>

Self-checking and fail-safe LSIs by intra-chip redundancy

The paper describes self checking LSIs realized by intra chip redundancy. Self checking comparators within the self checking LSI chips monitor the operation of redundant functional blocks to ensure the functionality of the LSIs. Spatial diversity and time diversity minimize correlated faults among redundant functional blocks, which may reduce fault detection coverage because of coincident faults. This approach allows advantage to be taken of the merits of todays most advanced LSI technologies. That is, higher performance, higher gate density, smaller dimensions, lower power consumption, and lower failure rate, in critical applications. In addition, this approach is well suited to contemporary design automation systems, and can enjoy their merits. The self checking LSIs were developed for experimental purposes and they will be applied to other fault tolerant applications in the future. In addition, the concept of intra chip redundancy is also employed for fail safe LSIs as one technique to ensure their fail safe features. The fail safe LSIs will be applied to train control systems in Japan in the near future.

An analog front-end LSI with on-chip isolator for V.90 56 kbps modems

This paper presents an isolated analog front-end (I-AFE) LSI with built-in isolation function for V.90, 56 kbps modems. The LSI has 1.5 kVrms. AC isolation and analog front-end functions within a 5 mm/spl times/4.5 mm die with 0.4 /spl mu/m SOI CMOS process and a 50 pin TSOP package. The on-chip isolation approach eliminates external isolation devices such as transformers or photo-couplers. A 100 Mbps transmission rate is attained by the on-chip isolator.

Node status monitoring and state transition mechanism for network centric X-by-Wire systems

X-by-Wire systems are expected to enhance vehicle driving performance and safety. Regarding the dependable and cost-effective electronic platform for X-by-Wire systems, the network centric architecture is proposed based on a concept of autonomous decentralized systems. This architecture enables that, if one node fails, the remaining normal nodes autonomously execute a backup control to maintain the system function. This mechanism is served by a membership functionality implemented in a middleware that is independent from applications so that this mechanism can be applied to any applications. Following the concept proposal, the node status monitoring algorithm is designed because it is essential to identify the failed node accurately to execute the autonomous backup control. In this paper, to obtain a stability of a system throughout a driving, a sequence for autonomous start up and stop of the system is newly designed applying the node status monitoring function.

Cost-Effective and Fault Tolerant Vehicle Control Architecture for X-by-Wire Systems (Part 2: Implementation Design)

X-by-Wire systems are expected to enhance vehicle driving performance and safety. This paper describes an electronic platform architecture for X-by-Wire systems that satisfies both cost-effectiveness and dependability. In the first part of this paper (Part 1), we have proposed a new electronic architecture based on a concept of autonomous decentralized systems. In the latter part (Part 2), the proposed architecture implementation to the actual vehicle control systems will be discussed. We clarify that, due to system level redundancy the proposed architecture provides, vehicle control systems can basically consist of low cost fail-silent nodes. Furthermore, for cost optimization, considering a tradeoff between hardware cost and fault detection coverage, we design a suitable hardware architecture for each node according to node function.

4-kV 100-Mbps monolithic isolator on SOI with multi-trench isolation for wideband network

We have developed a monolithic isolator that provides an isolation voltage of 4 kV and a signal transmission rate of 100 Mbps. Two circuit areas are isolated using 34 trenches on a bonded SOI with 3-µm-thick buried oxide. The inequality in the voltages applied to the trenches is reduced using polysilicon resistors parallel to the trenches, which increases the isolation voltage from 2.4 to 4.0 kV. The isolator consists of two series of high-voltage capacitors in which silicon on buried oxide and a third metal are used as electrodes. We have also developed a network interface LSI with 4-channel isolators, which provide 4-kV isolation and 100-Mbps transmission.

High Performance and Cost-Effective Electronic Controller Architecture for Powertrain Systems

Electronic controllers for powertrain systems are required to meet the demands for increased system performance and functionality at reasonable cost. It is indispensable to examine the solutions from a range of view points synthetically for cost optimization. This paper describes a cost-effective hardware and software architecture of the electronic controllers for powertrain systems. A new method for noise reduction of a switching regulator, and a low standby current wakeup solution are also discussed as further functions needed for high performance powertrain systems.

Dynamic autonomous redundancy management strategy for balanced graceful degradation

This paper proposes a redundancy management method, ARM (Autonomous Redundancy Management). The method dynamically allocates redundant computer modules to tasks by an autonomous algorithm based on shared fault information, considering the importance of the tasks necessary to balance their reliability margin. It allocates more computer modules to a task which is endangered because of the number of fault occurrences, or which is granted as a very important task requiring very high reliability.