Kotaro Shimamura

2.5 V CMOS circuit techniques for a 200 MHz superscalar RISC processor

Novel 2.5 V CMOS circuit techniques including a noise tolerant precharge (NTP) circuit and a leakless buffer circuit are applied to a floating point macrocell for a 200 MHz superscalar RISC processor. The NTP circuit has two advantages: high noise immunity and high speed. Floating point operations can be executed in a two cycle latency using the high speed NTP circuit. The leakless buffer circuit with NMOS transmission gate in 128 floating point registers makes possible both high integration and low power dissipation, since the circuit causes no leak current without precharging the number of read lines. The processor makes use of 0.3 /spl mu/m CMOS technology with a 2.5 V power supply and four metal layers. The floating point macrocell has 380 thousand transistors and dissipates 350 mW at 200 MHz. The peak performance of the floating point macrocell is 400 MFLOPS.

DART: Dependable VLSI test architecture and its implementation

Although many electronic safety-related systems require very high reliability, it is becoming harder and harder to achieve it because of delay-related failures, which are caused by decreased noise margin. This paper describes a technology named DART and its implementation. The DART repeatedly measures the maximum delay of a circuit and the amount of degradation in field, in consequence, confirms the marginality of the circuit. The system employing the DART will be informed the significant reduction of delay margin in advance of a failure and be able to repair it at an appropriate time. The DART also equips a technique to improve the test coverage using the rotating test and a technique to consider the test environment such as temperature or voltage using novel ring-oscillator-based monitors. The authors applied the proposed technology to an industrial design and confirmed its effectiveness and availability with reasonable resources.

A superscalar RISC processor with pseudo vector processing feature

A novel architectural extension, in which floating-point data are transferred directly from main memory to floating-point registers, has been successfully implemented in a superscalar RISC processor. This extension allows main memory access throughput of 1.2 Gbyte/s, and effective performance reaches 267 MFLOPS (89% of the peak performance) for typical floating-point applications. The processor utilizes 0.3-micron 4-level metal CMOS technology with 2.5 V power supply and contains 3.9 million transistors in 15.7 mm/spl times/15.7 mm die size. Only 4.5% of the die area is used for the extension. Pipeline stage optimization and scoreboard-based dependency check method allow the extension to be realized without affecting the operating frequency.

A 120-MHz BiCMOS superscalar RISC processor

A superscalar RISC processor contains 2.8 million transistors in a die size of 16.2 mm/spl times/16.5 mm, and utilizes 3.3 V/0.5 /spl mu/m BiCMOS technology. In order to take advantage of superscalar performance without incurring penalties from a slower clock or a longer pipeline, a tag bit is implemented in the instruction cache to indicate dependency between two instructions. A performance gain of up to 37% is obtained with only a 3.5% area overhead from our superscalar design. >

A Single-Chip Fail-Safe Microprocessor with Memory Data Comparison Feature

A single-chip fail-safe microprocessor has been developed. It contains two processor cores and realizes self-checking feature by comparing the processing results of the two processor cores. In order to overcome redundant input disagreement problem, two mechanisms have been implemented. The one is input data exchange mechanism used with bus comparison feature. The other is memory data comparison and copy mechanism. With the memory data comparison mechanism, input data comparison overhead can be reduced, which is especially useful for short period control task with many input data. The microprocessor utilizes 0.18mum CMOS process and integrates 512KB RAM and 25M transistors random logic in a 14.75mm x 14.75mm die. With the developed microprocessor, the size of a fault-tolerant controller can be reduced, which makes it easy to embed fault-tolerant controllers into equipments controlled

Node status monitoring and state transition mechanism for network centric X-by-Wire systems

X-by-Wire systems are expected to enhance vehicle driving performance and safety. Regarding the dependable and cost-effective electronic platform for X-by-Wire systems, the network centric architecture is proposed based on a concept of autonomous decentralized systems. This architecture enables that, if one node fails, the remaining normal nodes autonomously execute a backup control to maintain the system function. This mechanism is served by a membership functionality implemented in a middleware that is independent from applications so that this mechanism can be applied to any applications. Following the concept proposal, the node status monitoring algorithm is designed because it is essential to identify the failed node accurately to execute the autonomous backup control. In this paper, to obtain a stability of a system throughout a driving, a sequence for autonomous start up and stop of the system is newly designed applying the node status monitoring function.

A triple redundant controller which adopts the time-sharing fault recovery method and its application to a power converter controller

A novel fault recovery method, in which memory copy from a normal system to a fault detected system is executed in time-sharing fashion, has been implemented in a triple redundant controller. This method reduces data copy bandwidth required for recovery of the fault detected system, and allows non-stop fault recovery with only a little hardware overhead, even when the controller contains multiple processors and operates at a very short operating period. The developed controller contains triplicated processing units, each of which consists of seven 60 MIPS processor boards connected by a 30 MHz 4 byte bus. One processor board contains a bus arbiter, and each of the remaining six processor boards contains three sets of 100 Mbps two-way optical links, which can be utilized for inter-system memory copy as well as for connecting to 10 units. This controller has been applied to a power converter controller, and a 104 microsecond operating period was achieved.

Cost-Effective and Fault Tolerant Vehicle Control Architecture for X-by-Wire Systems (Part 2: Implementation Design)

X-by-Wire systems are expected to enhance vehicle driving performance and safety. This paper describes an electronic platform architecture for X-by-Wire systems that satisfies both cost-effectiveness and dependability. In the first part of this paper (Part 1), we have proposed a new electronic architecture based on a concept of autonomous decentralized systems. In the latter part (Part 2), the proposed architecture implementation to the actual vehicle control systems will be discussed. We clarify that, due to system level redundancy the proposed architecture provides, vehicle control systems can basically consist of low cost fail-silent nodes. Furthermore, for cost optimization, considering a tradeoff between hardware cost and fault detection coverage, we design a suitable hardware architecture for each node according to node function.

A fail-safe microprocessor using dual synthesizable processor cores

A chip level redundant self-checking fail-safe microprocessor has been developed using a 0.35 /spl mu/m CMOS embedded gate array. The microprocessor integrates two synthesizable processor cores and a self-checking comparator in a single chip. A full-custom processor core was transformed into each of the synthesizable cores for this purpose. Design methodologies suitable for reusing synthesizable processor cores has also been developed. Developed synthesizable processor cores and design methodologies reduce the cost of process migration of the chip. Migrating to the newer process improves the performance of the developed microprocessor with low development cost.