Takeo Matsuki

Low-resistance self-aligned Ti-silicide technology for sub-quarter micron CMOS devices

A low-resistance self-aligned Ti-silicide process featuring selective silicon deposition and subsequent pre-amorphization (SEDAM) is proposed and characterized for sub-quarter micron CMOS devices. 0.15-/spl mu/m CMOS devices with low-resistance and uniform TiSi/sub 2/ on gate and source/drain regions were fabricated using the SEDAM process. Non-doped silicon films were selectively deposited on gate and source/drain regions to reduce suppression of silicidation due to heavily-doped As in the silicon. Silicidation was also enhanced by pre-amorphization, using ion-implantation, on the narrow gate and source/drain regions. Low-resistance and uniform TiSi/sub 2/ films were achieved on all narrow, long n/sup +/ and p/sup +/ poly-Si and diffusion layers of 0.15-/spl mu/m CMOS devices. TiSi/sub 2/ films with a sheet resistance of 5 to 7 /spl Omega//sq were stably and uniformly formed on 0.15-/spl mu/m-wide n/sup +/ and p/sup +/ poly-Si. No degradation in leakage characteristics was observed in pn-junctions with TiSi/sub 2/ films. It was confirmed that, using SEDAM, excellent device characteristics were achieved for 0.15-/spl mu/m NMOSFETs and PMOSFETs with self-aligned TiSi/sub 2/ films.

0.15 /spl mu/m CMOS with high reliability and performance

0.15 /spl mu/m CMOSFETs with high reliability and performance have been realized. The acceptable power supply voltage V/sub cc/ was estimated to be 1.9 V. A reasonably short ring oscillator delay of 33 ps was obtained for the 1.9 V V/sub cc/, maintaining an 0.4 V threshold voltage. Anomalous surface state generation and V/sub TH/ shift for the pMOS were observed, though the degradation was less severe than the nMOS.<<ETX>>

Cu/poly-Si damascene gate structured MOSFET with Ta and TaN stacked barrier

A Cu/Si layered-gate-structured MOSFET with Ta and TaN stacked barrier layers fabricated using a Cu damascene process has been developed for high-performance and reliable Si ULSI devices. A sheet resistance of 0.5 ohm/sq. was achieved with a 0.25 /spl mu/m gate length. The Ta and TaN layers guarantee reliable gate oxide (7.5 nm) after 500/spl deg/C thermal processing in nitrogen with forming gas annealing.

Analysis of Processing Damage on a Ferroelectric SrBi2Ta2O9 Capacitor for Ferroelectric Random Access Memory Device Fabrication

For Ferroelectric random-access memory (FeRAM) device fabrication, it is important to control the processing ambience, especially the hydrogen in process, due to the reduction of ferroelectric oxides such as SrBi2Ta2O9 (SBT). We investigated processing damage to SBT capacitors during (1) the deposition of a cover film on SBT capacitors, (2) the fabrication of a contact hole by reactive ion etching (RIE), and (3) the photoresist mask removal. The O3-TEOS chemical vapor deposition (CVD) process for the deposition of a cover film causes less damage due to the presence of O3 a strong oxidizer. However, during the fabrication of contact holes in SBT capacitors, the plasma-gas species strongly affect the damage to the SBT capacitors. A less damaging process has been developed as follows: forming the contact hole by RIE with CF4 plasma gas instead of CHF3, and removing the photoresist by exposure to oxygen-radical downflow to eliminate hydrogen regeneration from the photoresist decomposition in the O2 plasma. After the process, the leakage current density and the remanent polarization are kept below 10-6 A/cm-2 and over 15 µC/cm2, respectively.

Crystalline-buffer-layer-aided (CBL) sputtering technique for mega-bit ferroelectric memory devices with SrBi/sub 2/Ta/sub 2/O/sub 9/ capacitors

A crystalline-buffer-layer-aided (CBL) SrBi/sub 2/Ta/sub 2/O/sub 9/ film deposition using two step sputtering technique has been developed through investigation of the interface structure between the Pt bottom electrode and SrBi/sub 2/Ta/sub 2/O/sub 9/. A layer having an amorphous structure, obtained by the Ar sputtering of the first step, leads to a depletion of Bi at the interface, whereas a crystalline structure, obtained by Ar/O/sub 2/ sputtering of the first step, inhibits such depletion. The two step sputtering deposition process is implemented to form a Bi-rich crystalline interface layer which improves the polarization characteristics. The remnant polarization values was improved up to 10 /spl mu/C/cm/sup 2/ by the modified deposition process.

A novel salicide process (SEDAM) for sub-quarter micron CMOS devices

A new salicide process, featuring selective silicon deposition and subsequent pre-amorphization (SEDAM), has been developed for sub-quarter micron CMOS devices. Non-doped silicon films were selectively deposited on gate and source/drain regions to avoid silicidation suppression due to heavily-doped As. Furthermore, silicidation was enhanced by pre-amorphization on the narrow gate and source/drain regions. TiSi/sub 2/ films, with a sheet resistance of /spl les/10 /spl Omega/sq., were stably and uniformly formed on all n/sup +/- and p/sup +/-poly-Si and source/drain diffusion layers for 0.15 /spl mu/m CMOS devices without degradation in the I-V characteristics.<<ETX>>

Low Temperature Recovery of Ru/(Ba, Sr)TiO3/Ru Capacitors Degraded by Forming Gas Annealing

A low temperature N2 post-annealing process was proposed to improve the degradation of Ru/(Ba, Sr)TiO3/Ru capacitors due to forming gas annealing. After N2 post-annealing at 300°C, the leakage current degraded by forming gas annealing was completely recovered to the initial level without affecting the SiO2 equivalent thickness of 0.51 nm. No degradation of the subthreshold characteristics of n-channel metal-oxide-semiconductor field effect transistors and N+P junction leakage current by the post-annealing was also confirmed. The Ru/(Ba, Sr)TiO3/Ru capacitor technology with this post-annealing process is suitable for dynamic random access memories in 0.13 µm generation and beyond.

Extendibility of High Mobility HfSiON Gate Dielectrics

1. Introduction HfSiON is considered the most promising candidate of gate dielectrics for hp65 node LSTP devices due to its high mobility [1-2]. Sub-1nm EOT high-k gate dielectrics are required for LOP devices in hp45 node and beyond [3]. However, the k-value of HfSiON is 16 at most. In order to obtain sub-1nm EOT, the physical thickness of HfSiON must be less than 2nm, even if the interfacial layer thickness is 0.5nm. Such a very small physical thickness causes enormous direct tunneling current. Therefore, the interfa-cial layer thickness has to be minimized to reduce the leakage current and EOT simultaneously. On the other hand, it is well known that there is a trade-off between carrier mobility and interfacial layer thickness [4]. The objective of this work is to fabricate sub-1nm EOT HfSiON by minimizing the interfacial layer thickness without fatal mobility reduction.

Separation of intrinsic and parasitic MOSFET parameters using a multiple built-in Kelvin test structure

A new MOSFET test structure built in multiple Kelvin patterns is used to evaluate scaled-down MOSFET characteristics through separation of intrinsic and parasitic parameters. Transistor characteristics and contact resistance of individual MOSFETs are simultaneously measured to clarify the direct correlation between fluctuation of MOSFET characteristics and that of parasitic contact resistance. MOSFET performance without parasitic interconnect resistance can be also measured to define intrinsic current drivability in a MOSFET fully scaled-down to less than sub-half-micrometers dimensions.

Gate-Last MISFET Structures and Process for Characterization of High-k and Metal Gate MISFETs

We propose new test device structures, Gate-Last-formed structures, which are suitable for fundamental study of high-k gate insulator or metal gate electrode MISFETs. The gate insulator and electrode stack is formed after local interconnect pads connected with source and drain. The gate stack is build in trench formed by dry and wet etching and is non-self-aligned to the source and drain. The wet etching restricts damage formation on the exposed Si surface underneath the trench. Electrical characteristics are measurable just after exposure of surface of the local interconnect pads without conventional Al wiring. This structure can provide methods both for fundamental evaluation and for material selection of new gate stack materials by investigation of MISFET characteristics. This is achieved with short TAT and avoiding contamination penalty to a fab.