Takahisa Eimori

Novel locally strained channel technique for high performance 55nm CMOS

A novel local strained channel (LSC) MOSFET has been fabricated by a stress control technique utilizing a strained poly silicon gate electrode. The residual compressive stress in arsenic (As) implanted polysilicon is induced by high temperature annealing of CVD SiO/sub 2/ cap with high tensile stress. On the other hand, boron (B) implanted poly silicon is free from stress. As a result, the only n-channel region is locally strained by the strained polysilicon electrode. The drain current of LSC nFETs is improved 15% compared to that of the conventional nFET without the degradation of pFET drain current. High performance 55nm CMOSFET is realized by simple process for LSC-structure.

An SOI-DRAM with wide operating voltage range by CMOS/SIMOX technology

For future ULSI DRAMs beyond the 256 Mb generation, several circuit techniques and memory cell structures have been proposed to meet the requirement of high performance at low voltage. These solutions frequently involve complicated processing steps and/or the ultimate limitations of current Si-MOS devices. DRAM on silicon on insulator (SOI) substrate is a more simple solution to the problem. Thin-film SOI structures with isolation by implanted oxygen (SIMOX) process are under investigation for SRAM and logic. A SOI-DRAM test device with 100 nm thick SOI film has been fabricated in 0.5 /spl mu/m CMOS/SIMOX technology. With this 64 kb SOI-DRAM the bit-line to memory cell capacitance ratio Cb/Cs is reduced by 25% compared with the reference bulk-Si DRAM, because of the decreased junction capacitance. RAS access time tRAC is 70 ns at 2.7 VVcc, as fast as the equivalent bulk-Si device at 4 VVcc. The clock timing in this DRAM is not optimized, so access time should improve with well-tuned clocks. The boosted-level generator with body-contact structure enhances the upper Vcc margin and the reduced body-effect of sense-amplifier transistors improves the lower Vcc margin. The SOI-DRAM has an operating Vcc range from 2.3 V to 4.0 V. >

A 34 ns 256 Mb DRAM with boosted sense-ground scheme

This boosted sense-ground (BSG) scheme extends the data retention time of a 256 Mb CMOS DRAM. This scheme features a L bitline level slightly boosted to suppress sub-threshold current of unselected memory-cell access transistors in the activated memory mats for the sake of the effective negative gate-source voltage (Vgs).<<ETX>>

An experimental 256-Mb DRAM with boosted sense-ground scheme

In developing the 256-Mb DRAM, the data retention characteristics must inevitably be improved. In order for DRAMs to remain the semiconductor device with the largest production volume in the 256-Mb era, we must develop a cost effective device with a small chip size and a large process tolerance. In this paper, we propose the BSG (boosted sense-ground) scheme for data retention and FOGOS (folded global and open segment bit-line) structure for chip size reduction. We have fabricated an experimental 256-Mb DRAM with these technologies and obtained a chip size of 304 mm/sup 2/ and a performance of 34 ns access time. >

16 Mb DRAM/SOI technologies for sub-1 V operation

Extra low voltage DRAM/SOI technologies were developed using (1) modified MESA isolation without parasitic MOS operation, (2) dual gate CMOS for low Vth control, (3) optimized layout using both body-tied and floating body MOSFETs, and (4) reduced Cb/Cs ratio. Completely redesigned low voltage scheme 16 MDRAM/SOI was successfully realized and functional operation was obtained at very low supply voltage below 1 V.

ULSI DRAM/SIMOX with stacked capacitor cells for low-voltage operation

An SOI-DRAM test device was fabricated on thin-film SOI (Silicon On Insulator) structure with 0.5 /spl mu/m CMOS/SIMOX (Separation by IMplanted OXygen) technology. Field-shield isolation and polysilicon pad techniques were introduced for the specific problems to thin-film SOI devices such as the floating body effects and increase of parasitic source/drain resistance, respectively. Keeping the thin-film SOI from etching off during DRAM cell processing was especially cared by using high-selectivity ECR etching technology. The bit-line capacitance of the experimental SOI-DRAM is reduced by 25% and the /RAS access time is 30% faster compared with the equivalent Bulk-Si DRAM. Low voltage DRAM operation down to 2 V range is also observed.<<ETX>>

Approaches to extra low voltage DRAM operation by SOI-DRAM

The newly designed scheme for a low-voltage 16 MDRAM/SOI has been successfully realized and the functional DRAM operation has been obtained at very low supply voltage below 1 V. The key process and circuit technologies for low-voltage/high-speed SOI-DRAM will be described here. The extra low voltage DRAM technologies are composed of the modified MESA isolation without parasitic MOS operation, the dual gate SOI-MOSFETs with tied or floating bodies optimized for DRAM specific circuits, the conventional stacked capacitor with increased capacitance by thinner dielectric film, and the other bulk-Si compatible DRAM structure. Moreover, a body bias control technique was applied for body-tied MOSFETs to realize high performance even at low voltage. Integrating the above technologies in the newly designed 0.5-/spl mu/m 16 MDRAM, high-speed DRAM operation of less than 50 ns has been obtained at low supply voltage of 1 V.

Novel low offset voltage diode using asymmetric threshold voltage MONOS-FET for next generation devices demanding low voltage operation

Novel diode with low offset voltage below 0.6V is proposed by using MONOS FET with asymmetric threshold voltage. Offset voltage of 0.3V can be achieved by suppressing off state current and reverse leakage current. This technique gives promising characteristics for next generation circuits with low voltage operation.