Noh-Yeal Kwak

Effect of Liner Oxide Densification on Stress-Induced Leakage Current Characteristics in Shallow Trench Isolation Processing

Controlling mechanical stress in the shallow trench isolation (STI) process is an increasing concern because it can affect circuit performance and yield. This paper presents the effect of liner oxide densification on the stress-induced junction leakage current in the STI process, compared to high density plasma (HDP) oxide densification before STI planarization. The simulation was performed for the trench isolation structure. It indicated that high temperature densification of the trench-tilled HDP oxide has a high probability of generating STI dislocations due to its inherently large mechanical stress and volume. The crystal defects and the mechanical stresses were significantly reduced by the introduction of liner oxide densification during STI processing; as a result, in the stress-induced junction, leakage characteristics were improved. The characteristics of standby current and column bit failure with regard to device yields have also been discussed.

Practical application of 2D dopant profiling by LV-SEM

Recently, scanning electron microscopy (SEM) has attracted much attention as a potential technique for quick and easy 2D dopant profiling in semiconductor devices. Dopant contrasts in SEM can be achieved at a low accelerating voltage range, which is called the LV-SEM technique. In this study, we have optimized the key parameters influencing dopant contrasts and evaluated the reliability of LV-SEM through comparison with secondary ion mass spectrometry (SIMS) in the multi-layered p-n junction specimen. The results obtained by LV-SEM were in very good agreement with those of other dopant profiling technique. Furthermore, we have demonstrated that the 2D dopant profiling by LV-SEM is available to real semiconductor devices such as MOSFETs, solar cells, power devices, etc.

Effect of annealing ambient on WSix(x=2.3) sidewall deformation and contact resistance in dichlorosilane-based W-polycide gate

To analyze the deformation of the WSix sidewall in a W-polycide gate, WSix(x=2.3) film was deposited by a modified dichlorosilane (SiH2Cl2, DCS) process that consisted of in situ monosilane (SiH4, MS)-based WSix nucleation, followed by DCS-based WSix deposition at 550 °C. Compared to the conventional DCS-based WSix film, the WSix film did not exhibit a W-rich interface facilitating the deformation and it showed similar structural property. Examination of deformation dependence on heat-treatment ambients suggested that a deformed region having a detrimental morphology was formed at the WSix sidewall during both nonoxidizing and oxidizing ambient annealings. It was revealed that the deformation in nonoxidizing and oxidizing ambient annealing resulted from the formation of a Si precipitate and W–Si–O compound at the WSix sidewall, respectively. In the case of N2 ambient preannealing at 600 °C for 30 min in the process of spacer oxide deposition, the deformation could be effectively suppressed by preventing the formation of Si precipitate at the WSix sidewall. The N2 ambient preannealing also improved the contact resistance of metal (Al/W plug with TiN/Ti barrier) on the W-polycide gate by promoting silicidation between Ti and excess Si in the WSix layer.To analyze the deformation of the WSix sidewall in a W-polycide gate, WSix(x=2.3) film was deposited by a modified dichlorosilane (SiH2Cl2, DCS) process that consisted of in situ monosilane (SiH4, MS)-based WSix nucleation, followed by DCS-based WSix deposition at 550 °C. Compared to the conventional DCS-based WSix film, the WSix film did not exhibit a W-rich interface facilitating the deformation and it showed similar structural property. Examination of deformation dependence on heat-treatment ambients suggested that a deformed region having a detrimental morphology was formed at the WSix sidewall during both nonoxidizing and oxidizing ambient annealings. It was revealed that the deformation in nonoxidizing and oxidizing ambient annealing resulted from the formation of a Si precipitate and W–Si–O compound at the WSix sidewall, respectively. In the case of N2 ambient preannealing at 600 °C for 30 min in the process of spacer oxide deposition, the deformation could be effectively suppressed by preventing t...

Precise Comparison of Two-dimensional Dopant Profiles Measured by Low-voltage Scanning Electron Microscopy and Electron Holography Techniques

Detailed comparison of low-voltage scanning electron microscopy and electron holography techniques for two-dimensional (2D) dopant profiling was carried out with using the same multilayered p-n junction specimen. The dopant profiles obtained from two methods are in good agreement with each other. It demonstrates that reliability of dopant profile measurement can be increased through precise comparison of 2D profiles obtained from various microscopic techniques.

Boron Transport Through Surface Channel pMOS Using W-poly Metal Gate Electrode Poly Si Doping Condition and Nitric Oxide Treatment Effects

This work considers boron transport through surface channel p-metal oxide semiconductors (pMOSs) using tungsten-poly metal gate electrode as a function of poly doping conditions and nitric oxide treatment by analyzing quasi-static capacitance-voltage curves and time-dependent dielectric breakdown characteristics obtained after applying the full thermal budget, especially including selective oxidation to prohibit tungsten oxidation. From the result obtained when nitrogen was implanted into undoped amorphous Si (α-Si), it can be recognized that out-diffusion of boron into tungsten and its nitride is negligible. Mixed implantations into undoped α-Si aggravates the gate depletion, whereas it has little relationship with boron penetration into the pMOS charnel. The abundance of dose in undoped α-Si facilitates the boron penetration, leading to gate oxide degradation and variation of the flatband voltage within the wafer as well as to the improvement of the gate depletion. From the comparison of the capacitance-voltage curve and the flatband voltage uniformity among experimental splits, it is found that the nitric oxide treatment retards the boron penetration into the pMOS channel effectively without significant degradation of the gate depletion.

Precise comparison of two-dimensional dopant profiles measured by electron holography and scanning capacitance microscopy

Detailed comparison of electron holography and scanning capacitance microscopy techniques for the 2D dopant profiling was carried out with using the same multilayered p-n junction specimen. The dopant profiles obtained from two methods are in good agreement with each other. It demonstrates that reliability of dopant profile measurement can be increased through precise comparison of 2D profiles obtained from various techniques.

Improvement of Poly Profile in Sub 30 nm Device By Damage Engineering and Tilted Implantation Method

Conventionally, P31 out‐gassing of floating gate by succeeding thermal processes happens in NAND FLASH that use floating gate structure, and this P31 out gassing causes degradation of PDR and cell characteristics in sub‐30 nm device. Usually, there is a method to keep PDR of in‐situ doped poly‐Si by increasing the concentration of P31, but this method also causes cell characteristics degradation by trap charge of tunnel oxide.So, we used another method of ion implantation to control P31 out‐gassing concentration of floating gate by declining effective channel length. If we use methods of low energy and zero tilt implantation, P31 Trap by dopant channeling occurs in tunnel oxide. So, we evaluated methods of low energy and tilted implantation. But in this case, there were poly loss and bending, due to the physical collision damage of implantation.Therefore, we evaluated the effects of tilt change, direction and temperature control of ion implantation to minimize poly loss of floating gate.

Failure Analysis of an Anomalous Subthreshold Current in Nano-Scale NAND Flash Memory

As the design rule of NAND-type memory decreases down to sub 100 nm tech regime, one of important problems is the control of the parasitic transistor phenomenon. The parasitic transistor which causes subthreshold kink at high substrate bias is a common phenomenon for STI (shallow trench isolation) technology, especially for isolation whose pitch needs to be shrunk. To resolve the degradation of device performance by the subthreshold hump, many process solution has been reported (Park, 2000). Furthermore, in the fabrication of nano-scale silicon device, accurate 2D failure analysis is one of the important fields to be solved. In this paper, we present the numerical simulation study of STI implant process factor to suppress anomalous hump effect and investigate feasibility of the application of scanning capacitance microscopy (SCM) and chemical staining method in 2D failure analysis of 70nm NAND flash device

Characterization of Parasitic Transistor Phenomenon in Nano‐scale NAND Flash Device by Blanket Tilt Implantation and Scanning Capacitance Microscopy

We present the application of scanning capacitance microscopy (SCM) in the failure analysis of 70nm NAND flash memory device. The SCM results are compared with chemical staining data and the feasibility of using the SCM are discussed. In order to suppress these anomalous hump characteristic, we perform numerical simulation study of trench sidewall implantation process and proposed the larger tilt angle implantation which can reduce dose factor of STI implant process for the DJBV (Drain Junction Breakdown Voltage) characteristic.

Improvement on the Reliability of Flash EEPROM by Annealing after Self-Aligned Source Dry Etching

This paper describes the effect of annealing on the characteristics of cycling endurance and charge retention in flash electronically erasable programmable read-only memory (EEPROM) fabricated by self-aligned source (SAS) dry etching process which was used for the shrinkage of cell size. The annealing process was used for the recovery and thickness compensation of the tunnel oxide edge at which severe plasma damage was accumulated during the SAS dry etching process. Through the analysis of cycling endurance, it was clarified that charge traps and structural defects were generated at the tunnel oxide edge during the SAS dry etching process and they induced the degradation of cycling endurance of memory cells, The characteristics of charge retention were improved due to the structural recovery and the thickness compensation of the tunnel oxide edge. An analysis of the results from the measurement of charge retention and the examination of the tunnel oxide edge with high resolution transmission electron microscope, indicates that the thickness compensation of the tunnel oxide edge affected more positively the reduction of tail bits than the structural recovery of the tunnel oxide edge.