Seung‐Woo Shin

Effect of Liner Oxide Densification on Stress-Induced Leakage Current Characteristics in Shallow Trench Isolation Processing

Controlling mechanical stress in the shallow trench isolation (STI) process is an increasing concern because it can affect circuit performance and yield. This paper presents the effect of liner oxide densification on the stress-induced junction leakage current in the STI process, compared to high density plasma (HDP) oxide densification before STI planarization. The simulation was performed for the trench isolation structure. It indicated that high temperature densification of the trench-tilled HDP oxide has a high probability of generating STI dislocations due to its inherently large mechanical stress and volume. The crystal defects and the mechanical stresses were significantly reduced by the introduction of liner oxide densification during STI processing; as a result, in the stress-induced junction, leakage characteristics were improved. The characteristics of standby current and column bit failure with regard to device yields have also been discussed.

Incorporation Effect of Thin Al2O3 Layers on ZrO2–Al2O3 Nanolaminates in a Composite Oxide–High-κ-Oxide Stack for Floating-Gate Flash Memory Devices

We demonstrate the electrical properties and reliability of ZrO2–Al2O3 nanolaminates as high-κ dielectric materials in a composite oxide–high-κ-oxide (OKO) stack for floating-gate flash memory devices with 40 nm technology nodes and beyond. The effects of incorporating thin Al2O3 layers into ZrO2 films as an inserting layer and a capping layer on the electrical properties and reliability are discussed. The incorporation of Al2O3 layers significantly improves the leakage current versus the capacitive-equivalent thickness (CET) and TDDB characteristics of the ZrO2–Al2O3 nanolaminate compared with those of the pure ZrO2 owing to the mismatch of the grain boundaries, improved resistance to silicon diffusion, and enhanced energetic-electron hardness of the high-κ film.

Boron Transport Through Surface Channel pMOS Using W-poly Metal Gate Electrode Poly Si Doping Condition and Nitric Oxide Treatment Effects

This work considers boron transport through surface channel p-metal oxide semiconductors (pMOSs) using tungsten-poly metal gate electrode as a function of poly doping conditions and nitric oxide treatment by analyzing quasi-static capacitance-voltage curves and time-dependent dielectric breakdown characteristics obtained after applying the full thermal budget, especially including selective oxidation to prohibit tungsten oxidation. From the result obtained when nitrogen was implanted into undoped amorphous Si (α-Si), it can be recognized that out-diffusion of boron into tungsten and its nitride is negligible. Mixed implantations into undoped α-Si aggravates the gate depletion, whereas it has little relationship with boron penetration into the pMOS charnel. The abundance of dose in undoped α-Si facilitates the boron penetration, leading to gate oxide degradation and variation of the flatband voltage within the wafer as well as to the improvement of the gate depletion. From the comparison of the capacitance-voltage curve and the flatband voltage uniformity among experimental splits, it is found that the nitric oxide treatment retards the boron penetration into the pMOS channel effectively without significant degradation of the gate depletion.

Optical Monitoring of Capacitance in Hemispherical Grain Polycrystalline Silicon for Advanced Dynamic Random Access Memory Application

A novel approach for monitoring the capacitance using optical data from the material characteristics of hemispherical grain (HSG) polycrystalline silicon film is reported. This noncontact optical method provides indirect measurement of electrical capacitance for advanced dynamic random access memory (DRAM) applications using HSG material. By a simple statistical analysis of the microscopic HSG structure, the actual electrical capacitance is estimated to better than 90% confidence level through correlation of the optically measured thickness and the void content of the HSG film. Data from broad band spectrop otometry (190-750 nm) with beam profile reflectometry are fitted in the context of the Bruggeman effective medium approximation (EMA) model to give HSG thickness and void content. The actual capacitance obtained from the electrical probe technique using an intrusive electrode on finished DRAM devices indicates good agreement with our approach.

Improvement of Poly Profile in Sub 30 nm Device By Damage Engineering and Tilted Implantation Method

Conventionally, P31 out‐gassing of floating gate by succeeding thermal processes happens in NAND FLASH that use floating gate structure, and this P31 out gassing causes degradation of PDR and cell characteristics in sub‐30 nm device. Usually, there is a method to keep PDR of in‐situ doped poly‐Si by increasing the concentration of P31, but this method also causes cell characteristics degradation by trap charge of tunnel oxide.So, we used another method of ion implantation to control P31 out‐gassing concentration of floating gate by declining effective channel length. If we use methods of low energy and zero tilt implantation, P31 Trap by dopant channeling occurs in tunnel oxide. So, we evaluated methods of low energy and tilted implantation. But in this case, there were poly loss and bending, due to the physical collision damage of implantation.Therefore, we evaluated the effects of tilt change, direction and temperature control of ion implantation to minimize poly loss of floating gate.

Si SET-based Flexible Multi-valued Half Adder Logic Cell

A single-electron-based half adder (HA) has been first fabricated on SOI wafer, which comprises of an XOR and a two-input AND gates. Three SET elements with two symmetrical side-gates for each were implemented with two MOSFETs. Grayscale contour plots of the HA output voltages and their voltage transfer characteristics display typical Sum and Carry-Out functions for binary, multi-valued (MV) and binary-MV mixed input voltages. Moreover, the HA functions convert into a subtraction function by using control gates of the SET in the AND gate. This flexible HA provides an arithmetic basis for the SET MV logic family of high density integration, operating with a ultra-low power.

Failure Analysis of an Anomalous Subthreshold Current in Nano-Scale NAND Flash Memory

As the design rule of NAND-type memory decreases down to sub 100 nm tech regime, one of important problems is the control of the parasitic transistor phenomenon. The parasitic transistor which causes subthreshold kink at high substrate bias is a common phenomenon for STI (shallow trench isolation) technology, especially for isolation whose pitch needs to be shrunk. To resolve the degradation of device performance by the subthreshold hump, many process solution has been reported (Park, 2000). Furthermore, in the fabrication of nano-scale silicon device, accurate 2D failure analysis is one of the important fields to be solved. In this paper, we present the numerical simulation study of STI implant process factor to suppress anomalous hump effect and investigate feasibility of the application of scanning capacitance microscopy (SCM) and chemical staining method in 2D failure analysis of 70nm NAND flash device

Single Electron-based Flexible Multi-valued Exclusive-OR Logic Gate

By using two symmetrical sidewall gates, we implemented a Si-based single-electron exclusive- OR (XOR) gate and reported on the first flexible multivalued (MV) functionality. A grayscale contour plot of the output voltages displays alternating high/low values as a function of two single-electron transistor (SET) input voltages. Their voltage transfer characteristics display typical XOR or XNOR gate function depending on input voltages for binary, MV, and binary-MV mixed-modes. This flexible two-input XOR gate, combined with the previously reported NAND/NOR gates, provide three basic arithmetic blocks for the SET-based MV logic gate family.

The incorporation effect of thin Al2O3 layers on ZrO2-Al2O3 nanolaminates in the composite oxide-high-K-oxide stack for the floating gate flash memory devices

Introduction Aggressive scaling of flash memory devices requires the inter-poly dielectrics (IPD) layer with high-K dielectric to enhance the coupling ratio [1-3]. However, most of high-K dielectrics except Al2O3 tend to be crystallized during deposition or subsequent thermal processes, forming grain boundaries which serve as leakage current paths and impurity diffusion paths [4-6]. Therefore, like HfAlO film for gate dielectric application, the incorporation of Al2O3 into high-K dielectric is needed to improve the leakage current characteristics and retard the impurity diffusion through the film [7,8]. In this paper, we fabricate ZrO2Al2O3 nanolaminates and present the effect of Al2O3 incorporation on their electrical properties and reliabilities in the composite oxide-high-K-oxide (OKO) stack.

Characterization of Parasitic Transistor Phenomenon in Nano‐scale NAND Flash Device by Blanket Tilt Implantation and Scanning Capacitance Microscopy

We present the application of scanning capacitance microscopy (SCM) in the failure analysis of 70nm NAND flash memory device. The SCM results are compared with chemical staining data and the feasibility of using the SCM are discussed. In order to suppress these anomalous hump characteristic, we perform numerical simulation study of trench sidewall implantation process and proposed the larger tilt angle implantation which can reduce dose factor of STI implant process for the DJBV (Drain Junction Breakdown Voltage) characteristic.