Nonel Thirer

Parallel Processing for a DSP Application using FPGA

In this paper we discuss a parallel architecture for an FPGA system including several embedded simple micro-processors (¿P), for a digital signal processing application (DSP). Each ¿P in the system has a different purpose and a separate code unit, but all the ¿Ps share the same data unit. The architecture of the ¿P can vary in type ¿ it may be designed in the traditional form of a ¿P, or as a FIR filter, a video pattern generator and so on. Such systems can constitute a good solution when the DSPs main process can be divided into several processes. Every ¿P can be reprogrammed to perform more than one function, and a superscalar operation mode can be introduced and controlled by the programmer. This type of platform was designed and experimented for an audio synthesizer system.

A FPGA implementation of hardware based accelerator for a generic algorithm

Finding an optimum function is not only a theoretical mathematical problem but also a particular engineering problem. Many aspects in the electrical and electronics field (by example: image processing, filter matching, optimization of network parameters, resources allocation) can be solved by finding a target function and his minimum or maximum. For such problems, usually an analytical solution is not available and iterative algorithms are used. An Algorithm based of “Brute Force” require a very large number of iterations, such be a big disadvantage, especially when the algorithm is used for NP (Nondeterministic Polynomial time) problems where complexity and time to solve are incising exponentially with a number of an input parameters. More efficient algorithm is a Genetic Algorithm (GA), which imitates the biological evolution process, finding the solution by mechanism of “natural selection”, where the strong has higher chances to survive. Appling such algorithm in real time systems requires special approach due to variable number of iterations preformed until a solution is found. In this paper, we present the implementation for a hardware-based accelerator for a GA that solves a specific NP task. The accelerator implemented on a FPGA to provide a high-speed solution for this particular problem, for using in a real time system. An enhanced GA algorithm to solve the TSP problem presented and results obtained by writing a complete C simulation are analyzed. Algorithms and VHDL programs for PRNG and fixed point real numbers arithmetics, required for full FPGA implementation of a GA algorithm, and developed in accordance with our target Altera development board, are presented also. In addition, some possible solutions to improve our solution are analyzed.

Improvement of pipelines implementations in FPGA designs

System architecture has a significant impact on software performance. In this manuscript, a method to increase the performance of the microprocessors and FPGA based systems using pipeline processing, is presented. An improved implementation using this concept, for image and display processing, providing real time vision applications, is described.

A pipelined FPGA implementation of an encryption algorithm based on genetic algorithm

With the evolution of digital data storage and exchange, it is essential to protect the confidential information from every unauthorized access. High performance encryption algorithms were developed and implemented by software and hardware. Also many methods to attack the cipher text were developed. In the last years, the genetic algorithm has gained much interest in cryptanalysis of cipher texts and also in encryption ciphers. This paper analyses the possibility to use the genetic algorithm as a multiple key sequence generator for an AES (Advanced Encryption Standard) cryptographic system, and also to use a three stages pipeline (with four main blocks: Input data, AES Core, Key generator, Output data) to provide a fast encryption and storage/transmission of a large amount of data.

Distribution Laws of Small Size Samples. Metrological Implementation

In this paper is exposed an original technique to determine the empirical probability density function (pdf) and the empirical cumulative distribution function (cdf) and to estimate moments of any order, for a small size random sample (m=3 - 10) of a continuous random variable (rv). The efficiency of the proposed method is checked up by applying the Kolmogorov-Smirnov test to several series of pseudorandom numbers heaving known distribution laws. In the last part of the paper are presented the advantages of our method for distribution determination in metrological measurements, specially for destructive or expensive measurements.

An FPGA controller for the image transceiver device

A CMOS liquid crystal based image transceiver device (ITD) is under development at both the Holon Institute of Technology and Ben Gurion University. This device. as its name suggests, both receives and displays images by using a dual-function array of imager and display elements. An FPGA controller chip is under development for this chip. The uniqueness of this controller is its capability to control both the imaging and the display functions of the ITD chip. The FPGA controller, based on the Xilinx Virtex II architecture, allows the ITD array to perform real time vision modes of image capture, image display, as well as image superposition and its display. In addition, the chip is designed to control the ADC and DAC circuits of the ITD chip so as to allow data transfer between the ITD chip and an external computer for subsequent processing. In this work the FPGA controller as well as the ITD system and its associated control units, are described.

Modeling vechicles and mobile robots

Locomotion systems of wheeled mobile robots and electric cars consist of a rectangular or a circular platform, one or two drive wheels and one or two free wheels (when a unicycle type robot has only one drive wheel). The wheels may be fixed, steering, castor or Swedish. The steering wheel has a rotation about the vertical axle, passing through the center of the wheels. The castor wheels vertical rotation axle is different than the center of the wheel. The paper presents a unitary model of the unicycle type mobile robots (car type) and of the vehicle robots - electric cars with one or more trailers. The mobile robot car type is foreseen a unicycle mobile robot with a trailer. For the mobile robots with trailers, the correlation between the rotation angle of the truck or of the trailer and the steering angle, and also the stabilizing conditions are demonstrated. An FPGA based implementation for this model is presented. The input data is provided by the user or is generated by a special programmed unit. The output data is displayed and provided to a DtoA external circuit.

Considerations concerning an image transceiver system design

In this presentation, several options for implementing an Image Transceiver System operating in real time are analyzed. These include: the implementation of a multi chip system (including Display, Imager and Controller/Processor chips) versus a single chip embedded system. The logical and physical aspects of a single chip, two chip- and three chip-implementation are analyzed. The parallel and serial data transfer methods are analyzed for each case.

Design of low cross-talk image transceiver device and controller circuitry

An image transceiver device (ITD) is under development at the Holon Institute and Ben Gurion University. The device, capable of performing imaging and display functions in a single chip, is based on a combination of CMOS and LCOS technologies. Its main applications include smart goggles and vision enhancement. We report on studies to reduce the cross-talk in the ITD chip. These studies, which cover an n-well, a twin-well and a deep p-well structure, indicate that the deep p-well structure is the preferred approach resulting in the lowest cross-talk level of all three candidates. The second area studied was a novel design of an FPGA chip required in order to control the unique imager-display circuitry of the ITD. Details of the controller circuitry and its functions are presented.