Norikatsu Takaura

A 512kB Embedded Phase Change Memory with 416kB/s Write Throughput at 100μA Cell Write Current

An experimental 512kB embedded PCM uses a current-saving architecture in a 0.13μm 1.5V CMOS. The write scheme features a low-write-current resistive device and achieves 416kB/s write-throughput at 100muA cell current. A charge-transfer direct-sense scheme has a 16b parallel read access time of 9.9ns in an array drawing 280μA. A standby voltage scheme suppresses leakage current in the cell current path and increases the measured PCM cell resistance from 3 to 33MΩ.

Phase change RAM operated with 1.5-V CMOS as low cost embedded memory

This paper describes a phase change (PC) RAM operated at the lowest possible voltage, 1.5 V, with a CMOS memory array, using PC material with the lowest RESET current. We discuss the margins for reset/set/read operations based on measurement results and identified that it is impossible to distinguish between reset/set operations by controlling the bit-line voltage. We propose a new tri-level voltage word-line control (3LV-WL) scheme to clearly operate set operations. Moreover, we investigated the read disturb operation and developed a new reduced-actual-read-access (RA2) scheme to attain 500 times the read retention time. We also developed a source line control (SLC) scheme to attain an 18% smaller cell size and a 19-F/sup 2/ memory cell with enough reset current to clearly reset the PC material. With the application of these approaches, we established reset/set/read operations with the lowest possible voltage, 1.5 V with logic CMOS, for a low-cost embedded memory with a few additional masks.

A GeSbTe phase-change memory cell featuring a tungsten heater electrode for low-power, highly stable, and short-read-cycle operations

This paper presents a GeSbTe memory cell with a tungsten heater electrode. The cell has the lowest reset current (50 /spl mu/A) ever reported for a phase-change memory device. The factors responsible for re-amorphization, which increased the instability of crystallization are shown. The GeSbTe cell in this work offers a read-time within 2 nsec, which allows 200 MHz-chip operation with negligible effects of read disturbance.

Ta2O5 Interfacial Layer between GST and W Plug enabling Low Power Operation of Phase Change Memories

A novel memory cell for phase-change memories (PCMs) that enables low-power operation has been developed. Power (i.e., current and voltage) for the cell is significantly reduced by inserting a very thin Ta2O5 film between GeSbTe (GST) and a W plug. The Ta2O5 interfacial layer works not only as a heat insulator enabling effective heat generation in GST but also as an adhesion layer between GST and SiO2 underneath. Nonetheless, sufficient current flows through the interfacial layer due to direct tunneling. A low programming power of 1.5 V/100 muA can therefore be obtained even on a W plug with a diameter of 180 nm fabricated using standard 0.13-mum CMOS technology. In addition, the uniformity and repeatability of cell resistance are excellent because of the inherently stable Ta2O5 film properties

GeTe sequences in superlattice phase change memories and their electrical characteristics

We studied GeTe structures in superlattice phase change memories (superlattice PCMs) with a [GeTe/Sb2Te3] stacked structure by X-ray diffraction (XRD) analysis. We examined the electrical characteristics of superlattice PCMs with films deposited at different temperatures. It was found that XRD spectra differed between the films deposited at 200 °C and 240 °C; the differences corresponded to the differences in the GeTe sequences in the films. We applied first-principles calculations to calculate the total energy of three different GeTe sequences. The results showed the Ge-Te-Ge-Te sequence had the lowest total energy of the three and it was found that with this sequence the superlattice PCMs did not run.

Doped In-Ge-Te Phase Change Memory Featuring Stable Operation and Good Data Retention

We have fabricated a phase change memory using doped In-Ge-Te to improve the data retention required for industrial and automotive use. This chalcogenide features higher thermal stability as well as denser texture and improved adhesion. The memory cell using doped In-Ge-Te provided a larger read margin and better data retention than conventional Ge2Sb2Tes, and we demonstrated 10-year retention at temperatures above 150degC, which is the highest temperature ever reported.

Oxygen-doped gesbte phase-change memory cells featuring 1.5 V/100-/spl mu/A standard 0.13/spl mu/m CMOS operations

We demonstrated the operation of phase-change memory cells that enabled 1.5-V/100-muA programming through a tungsten-bottom-electrode contact with a diameter of 180 nm. This is the lowest power ever reported. This was achieved with oxygen-doped GeSbTe, and resulted from the high electric resistance of the germanium oxides in this material. Germanium oxides were also estimated to restrain the growth of crystal in GeSbTe, and our cells maintained a 10-year thermal lifetime at 100 degC

Characterization of In20Ge15Sb10Te55 Phase Change Material for Phase Change Memory with Low Power Operation and Good Data Retention

An indium-incorporated germanium–antimony–telluride material, In20Ge15Sb10Te55 (IGST), was investigated as a recording material for phase change memory. The crystallization temperature of IGST was 226 °C, which is 75 °C higher than that of conventional GST. The reset current of the device using IGST was about 10 mA for a plug 180 nm in diameter, which enabled a low-power operation, compared with the GST-based device. A cycle endurance of up to 1.5×104 was achieved. The data retention was estimated to be 10 years at 145 °C. These data clearly show that IGST exhibits promising characteristics as a recording material for phase change memory.

Superlattice Phase Change Memory Fabrication Process for Back End of Line Devices

The superlattice film with the periodical thin film layers of Sb2Te3/GeTe used as a phase change memory was studied for deposition in the crystal phase. We successfully fabricated the superlattice structure with the sputtering temperature of 200 °C. Moreover, the pillar structure with the size of 70 nm was dry-etched using a HBr/Ar gas mixture.

1T-1R pillar-type topological-switching random access memory (TRAM) and data retention of GeTe/Sb 2 Te 3 super-lattice films

A 1T-1R pillar-type “topological-switching RAM” (TRAM) and the data retention of GeTe/Sb₂Te₃ super-lattice were investigated. Reset voltage of TRAM, 2 V, was 40 % of that of the conventional PCM with Ge₂Sb₂Te₅. From data retention evaluation, the TRAM was found to endure the retention at 260 °C for 18 hours.