Riichiro Takemura

2Mb Spin-Transfer Torque RAM (SPRAM) with Bit-by-Bit Bidirectional Current Write and Parallelizing-Direction Current Read

A 1.8V 2Mb spin-transfer torque RAM chip using a 0.2mum logic process with an MgO tunneling barrier cell demonstrates the circuit technologies for potential low-power non-volatile RAM, or universal memory. This chip features an array scheme with bit-by-bit bidirectional current write to achieve proper spin-transfer torque writing in 100ns, and parallelizing-direction current reading with a low-voltage bit-line that leads to 40ns access time.

Spin-transfer torque RAM technology: Review and prospect

Abstract Non-volatile RAM (NV-RAM) enables instant-on/off computing, which drastically reduces power consumption. One of the most promising candidates for NV-RAM technology is the spin-transfer torque RAM (SPRAM) based on magnetic tunnel junction (MTJ) device technology. This paper reviews the development of MTJ device technology and formulates considerations regarding its memory application, including SPRAM memory cell structure and operation, write voltage limitation, and thermal stability. At the circuit level, a disruptive read operation for future large integration scale is described. A 4 F 2 memory cell and a multi-bit cell approach are also presented. Finally, the potential value of instant-on/off computing through NV-RAM and its impact are explored.

A multi-level-cell spin-transfer torque memory with series-stacked magnetotunnel junctions

We first report a multi-level-cell (MLC) spin-transfer torque memory (SPRAM) with series-connected magnetotunnel junctions (MTJs). The series MTJs (with different areas) show multi-level resistances by a combination of their magnetization directions. A four-level operation by spin-transfer-torque writing was experimentally demonstrated. A scheme for the write/read operation of the MLC SPRAM was also presented.

Current-Induced Magnetization Switching in MgO Barrier Magnetic Tunnel Junctions With CoFeB-Based Synthetic Ferrimagnetic Free Layers

We investigated the effect of using a synthetic ferrimagnetic (SyF) free layer in MgO-based magnetic tunnel junctions (MTJs) on current-induced magnetization switching (CIMS), particularly for application to spin-transfer torque random access memory (SPRAM). The employed SyF free layer had a Co₄₀Fe₄₀B₂₀/Ru/Co₄₀Fe₄₀B₂₀and Co₂₀Fe₆₀B₂₀/Ru/Co₂₀Fe₆₀B₂₀structures, and the MTJs (100 times (150-300) nm²) were annealed at 300 ^degC. The use of SyF free layer resulted in low intrinsic critical current density (<i>J</i> _c0) without degrading the thermal-stability factor (<i>E</i>/<i>k</i> _B <i>T</i>, where <i>E</i>, <i>k</i> _B, and <i>T</i> are the energy potential, the Boltzmann constant, and temperature, respectively). When the two CoFeB layers of a strongly antiferromagnetically coupled SyF free layer had the same thickness, <i>J</i> _c0 was reduced to 2-4 times10⁶ A/cm². This low <i>J</i> _c0 may be due to the decreased effective volume under the large spin accumulation at the CoFeB/Ru. The <i>E</i>/<i>k</i> _B <i>T</i> was over 60, resulting in a retention time of over ten years and suppression of the write current dispersion for SPRAM. The use of the SyF free layer also resulted in a bistable (parallel/antiparallel) magnetization configuration at zero field, enabling the realization of CIMS without the need to apply external fields to compensate for the offset field.

Phase change RAM operated with 1.5-V CMOS as low cost embedded memory

This paper describes a phase change (PC) RAM operated at the lowest possible voltage, 1.5 V, with a CMOS memory array, using PC material with the lowest RESET current. We discuss the margins for reset/set/read operations based on measurement results and identified that it is impossible to distinguish between reset/set operations by controlling the bit-line voltage. We propose a new tri-level voltage word-line control (3LV-WL) scheme to clearly operate set operations. Moreover, we investigated the read disturb operation and developed a new reduced-actual-read-access (RA2) scheme to attain 500 times the read retention time. We also developed a source line control (SLC) scheme to attain an 18% smaller cell size and a 19-F/sup 2/ memory cell with enough reset current to clearly reset the PC material. With the application of these approaches, we established reset/set/read operations with the lowest possible voltage, 1.5 V with logic CMOS, for a low-cost embedded memory with a few additional masks.

A GeSbTe phase-change memory cell featuring a tungsten heater electrode for low-power, highly stable, and short-read-cycle operations

This paper presents a GeSbTe memory cell with a tungsten heater electrode. The cell has the lowest reset current (50 /spl mu/A) ever reported for a phase-change memory device. The factors responsible for re-amorphization, which increased the instability of crystallization are shown. The GeSbTe cell in this work offers a read-time within 2 nsec, which allows 200 MHz-chip operation with negligible effects of read disturbance.

A disturbance-free read scheme and a compact stochastic-spin-dynamics-based MTJ circuit model for Gb-scale SPRAM

A magnetic-tunnel-junction (MTJ) circuit model, which considers spin dynamics under finite temperature, electrical bias, a stochastic process, and spin-transfer torque, was developed. Switching behaviors simulated by this model were verified by experimental measurements. Moreover, a disturbance-free read scheme for Gbit-scale spin-transfer torque RAM (SPRAM) was also developed. The feasibility of this scheme was confirmed by circuit simulation using the model and on-chip measurement of switching probability.

A novel SPRAM (SPin-transfer torque RAM) with a synthetic ferrimagnetic free layer for higher immunity to read disturbance and reducing write-current dispersion

A novel SPRAM (spin-transfer torque RAM) consisting of MgO-barrier-based magnetic tunnel junctions (MTJs) with a synthetic ferrimagnetic (SyF) structure in a free layer was demonstrated for both higher immunity to read disturbance and a sufficient margin between the read and write currents. Since magnetization of the free layer becomes stable against thermal fluctuation with increasing thermal-stability factor E/kBT, the SyF free layer of the MTJs realized a magnetic information retention of over 10 years due to its high E/kBT of 67. Furthermore, it was found that the SyF free layer has an advantage of reducing dispersion of write-current density Jc, which is necessary for securing an adequate margin between the read and write currents.

A multi-gigabit DRAM technology with 6F/sup 2/ open-bit-line cell distributed over-driven sensing and stacked-flash fuse

To cope with difficult device miniaturization in the multi-gigabit era, memory cells smaller than the traditional 8F/sup 2/ folded bitline (BL) cell are needed. A 6F/sup 2/ trench capacitor folded-BL cell has been recently described. However, it needs not only additional tight-pitch layers to create a vertically folded-BL arrangement, but also a vertical transistor. The 6F/sup 2/ open-BL cell enabling a simple planar transistor is another candidate as its inherently large imbalance noise between pairs of BLs is reduced. Low-voltage, high-speed array operation is essential in the multi-gigabit era. A conventional non-over-driven sensing scheme cannot achieve a high enough speed at an array voltage below 1.6 V, because the threshold voltage (Vth) cannot be reduced <0.1 V to obtain a low enough stand-by current. Distributed over-driven sensing enables a higher speed due to reduced voltage loss caused by distributed drivers combined with meshed power lines. Consequently, compared with the conventional schemes, the sensing time for a 1.2 V array voltage necessary for the 1 Gb generation decreased by 6.9 ns and 2.0 ns. Hence, this sensing scheme is promising for array voltages below 1.0 V in multi-gigabit memory. In multi-gigabit DRAMs, redundancy for degraded cells after packaging is a major concern. To overcome this a scheme is adopted which features a stacked flash fuse composed of three series flash fuses utilizing standard CMOS transistors without any additional process steps. Thus this technology can be used to fabricate a 0.13 μm 180 mm/sup 2/ 1 Gb DRAM assembled in a 400-mil package.

Oxygen-doped gesbte phase-change memory cells featuring 1.5 V/100-/spl mu/A standard 0.13/spl mu/m CMOS operations

We demonstrated the operation of phase-change memory cells that enabled 1.5-V/100-muA programming through a tungsten-bottom-electrode contact with a diameter of 180 nm. This is the lowest power ever reported. This was achieved with oxygen-doped GeSbTe, and resulted from the high electric resistance of the germanium oxides in this material. Germanium oxides were also estimated to restrain the growth of crystal in GeSbTe, and our cells maintained a 10-year thermal lifetime at 100 degC