Norma Rodriguez

Automatic hotspot classification using pattern-based clustering

This paper proposes a new design check system that works in three steps. First, hotspots such as pinching/bridging are recognized in a product layout based on thorough process simulations. Small layout snippets centered on hotspots are clipped from the layout and similarities between these snippets are calculated by computing their overlapping areas. This is accomplished using an efficient, rectangle-based algorithm. The snippet overlapping areas can be weighted by a function derived from the optical parameters of the lithography process. Second, these hotspots are clustered using a hierarchical clustering algorithm. Finally, each cluster is analyzed in order to identify the common cause of failure for all the hotspots in that cluster, and its representative pattern is fed to a pattern-matching tool for detecting similar hotspots in new design layouts. Thus, the long list of hotspots is reduced to a small number of meaningful clusters and a library of characterized hotspot types is produced. This could lead to automated hotspot corrections that exploit the similarities of hotspots occupying the same cluster. Such an application will be the subject of a future publication.

Clustering and pattern matching for an automatic hotspot classification and detection system

This paper provides details of the implementation of a new design hotspot classification and detection system, and presents results of using the system to detect hotspots in layouts. A large set of hotspot snippets is grouped into a small number of clusters containing geometrically similar hotspots. A fast incremental clustering algorithm is used to perform this task efficiently on very large datasets. Each cluster is analyzed to produce a characterization of a class of hotspots, and a pattern matcher is used to detect hotspots in new design layouts based on the hotspot class descriptions.

Developing DRC Plus Rules through 2D Pattern Extraction and Clustering Techniques

As technology processes continue to shrink and aggressive resolution enhancement technologies (RET) and optical proximity correction (OPC) are applied, standard design rule constraints (DRC) sometimes fails to fully capture the concept of design manufacturability. DRC Plus augments standard DRC by applying fast 2D pattern matching to design layout to identify problematic 2D patterns missed by DRC. DRC Plus offers several advantages over other DFM techniques: it offers a simple pass/no-pass criterion, it is simple to document as part of the design manual, it does not require compute intensive simulations, and it does not require highly-accurate lithographic models. These advantages allow DRC Plus to be inserted early in the design flow, and enforced in conjunction with standard DRC. The creation of DRC Plus rules, however, remains a challenge. Hotspots derived from lithographic simulation may be used to create DRC Plus rules, but the process of translating a hotspot into a pattern is a difficult and manual effort. In this paper, we present an algorithmic methodology to identify hot patterns using lithographic simulation rather than hotspots. First, a complete set of pattern classes, which covers the entire design space of a sample layout, is computed. These pattern classes, by construction, can be directly used as DRC Plus rules. Next, the manufacturability of each pattern class is evaluated as a whole. This results in a quantifiable metric for both design impact and manufacturability, which can be used to select individual pattern classes as DRC Plus rules. Simulation experiment shows that hundreds of rules can be created using this methodology, which is well beyond what is possible by hand. Selective visual inspection shows that algorithmically generated rules are quite reasonable. In addition to producing DRC Plus rules, this methodology also provides a concrete understanding of design style, design variability, and how they affect manufacturability.

Hotspot Prevention Using CMP Model in Design Implementation Flow

As part of copper (Cu) damascene manufacturing process, chemical mechanical polishing (CMP) has been applied to keep the uniformity of metal thickness, and the planarity of chip/wafer to accommodate todays shrinking lithography process window. CMP is a process that heavily depends on the metal width and density, and there is a strong interaction between design and CMP process. Dummy fills (tiling) are routinely applied to the design files to keep metal density uniform. However, due to complex natures of CMP process (pad, slurry and metal/oxide interaction, long range and multi-level effects), CMP related hotspots are often observed in the manufacturing process. CMP related issues such as Cu pooling/bridging and excessive thickness variation will have a major impact on chip yield and circuit timing and performance. Thus it is essential to correct those hotspots during circuit design stage for better yield and performance. In this paper we will introduce the use of an accurate physical based model to simulate CMP process on a full chip level and detect CMP related hotspots. We will show by using cadence CMP predictor (CCP), hotspots that are related to the tiling approach were detected. The CMP model can then be used to assist developing optimal tiling approach and reduce or eliminate CMP related hotspots, hence help to enhance the yield of the designs. The unique capability of detecting CMP related hotspot accurately has made CCP a valuable tool in the design flow to improve yield and performance.

An up-stream design auto-fix flow for manufacturability enhancement

Although many physical limitations have been reached in modern micro-lithography, printed critical dimensions continue to shrink according to the International Technology Roadmap for Semiconductors (ITRS). To meet the demands imposed by this guideline, the traditional separation between design and manufacturing communities is being bridged. Many EDA tools package manufacturing data for delivery into established simulation engines for design verification. However, none of them provide practical implementations of design optimizations at an early stage in the design flow. This paper presents an automated layout modification flow for metal layers with the goal of enhancing manufacturability. It can easily be deployed in a current custom design flow in a way that is visible to designers. The result of this scheme is improvements to process windows and yield, while minimizing circuit performance detractors. The flow is verified through analyses of both the impact on circuit performance and the benefit to manufacturability. It has been implemented in a state-of-the-art 65 nm chip design. Both silicon yield and electrical performance data are currently being collected and analyzed

DRCPlus in a router: automatic elimination of lithography hotspots using 2D pattern detection and correction

As technology processes continue to shrink, standard design rule checking (DRC) has become insufficient to guarantee design manufacturability. DRCPlus is a powerful technique for capturing yield detractors related to complex 2D situations1,2. DRCPlus is a pattern-based 2D design rule check beyond traditional width and space DRC that can identify problematic 2D configurations which are difficult to manufacture. This paper describes a new approach for applying DRCPlus in a router, enabling an automated approach to detecting and fixing known lithography hotspots using an integrated fast 2D pattern matching engine. A simple pass/no-pass criterion associated with each pattern offers designers guidance on how to fix these problematic patterns. Since it does not rely on compute intensive simulations, DRCPlus can be applied on fairly large design blocks and enforced in conjunction with standard DRC in the early stages of the design flow. By embedding this capability into the router, 2D yield detractors can be identified and fixed by designers in a push-button manner without losing design connectivity. More robust designs can be achieved and the impact on parasitics can be easily assessed. This paper will describe a flow using a fast 2D pattern matching engine integrated into the router in order to enforce DRCPlus rules. An integrated approach allows for rapid identification of hotspot patterns and, more importantly, allows for rapid fixing and verification of these hotspots by a tool that understands design intent and constraints. The overall flow is illustrated in Figure 1. An inexact search pattern is passed to the integrated pattern matcher. The match locations are filtered by the router through application of a DRC constraint (typically a recommended rule). Matches that fail this constraint are automatically fixed by the router, with the modified regions incrementally re-checked to ensure no additional DRCPlus violations are introduced.

Variation-aware analysis: savior of the nanometer era?

VLSI engineers have traditionally used a variety of CAD analysis tools (e.g. SPICE) to deal with variability. As we go into deep sub micron issues, the analysis is becoming harder due to many secondary effects becoming primary. Panelists will debate the variability trend and present the order of importance of many variability trends (Vdd, Vt, interconnect, Leff, gate width) and their impact on design tools and methodologies. What new design tools, new modeling methodologies, and new (or old) design styles will combine to address variability? Will conservative design to accommodate variability halt the progress of Moores law? Is life as we know it over, or are we facing an opportunity for innovation in tools and design that will move us forward over the barriers that technology has placed in our path?

A pattern-driven design regularization methodology

Pattern matching tools have become increasingly common in physical design flows for verification and layout analysis. Recently developed topological-based pattern matching engines offer several advantages over conventional three-value logic implementations. In this paper the use of such topological engines is explored for measuring physical design regularity, driving improvements in overall regularity, and for implementing targeted enhancements for suboptimal layout configurations.

The complexity of fill at 28nm and beyond

The history of dummy fill in semiconductor design goes back many generations of technology development. From its start with planarization requirements, fill needs have expanded across many wafer process manufacturing steps. They include lithography, etch, deposition, surface anneal, and device performance with stress analysis. Modern EDA tools have advanced to automatically place dummy shapes to meet these new requirements. These include placing multi-layer cell constructs, and multi-layer analysis during placement. New fill requirements have affected downstream flows such as extraction and timing analysis, physical verification, and RET flows. Further enhancements to fill tools and flows are under development to meet the total DFM needs for the next generations of chips.

Integration of OPC and mask data preparation

As design rules shrink aggressively while the wavelength reduction in the exposure equipment cannot keep up, extensive usage of resolution enhancement techniques (RET) has complicated the generation and handling of mask writing data. Consequently, file size growth and computing times for mask data preparation rise beyond feasibility. In order to address these issues, an integrated flow has been developed. It starts out with the gds-file delivered by the backend of design and combines optical proximity correction, design rule and mask process rule verification, and all other necessary steps for mask data preparation into a single flow. The benefits of this strategy are time savings in data processing and handling, the elimination of intermediate files, and the elimination of data format interface issues. Since the new flow takes full advantage of the design hierarchy, file sizes shrink considerably and the whole data preparation infrastructure can be simplified. The paper will describe the transition to the new flow and quantify the benefits.