Luigi Capodieci

Advanced timing analysis based on post-OPC extraction of critical dimensions

While performance specifications are verified before sign-off for a modern nanometer scale design, extensive application of optical proximity correction substantially alters the layout introducing systematic variations to the simulated and verified performance. As a result, actual on-silicon chip performance is quite different from sign-off expectations. This paper presents a new methodology to provide better estimates of on-silicon performance. The technique relies on the extraction of residual OPC errors from placed and routed full chip layouts to derive actual (i.e., calibrated to silicon) CD values that are then used in timing analysis and speed path characterization. This approach is applied to a state-of-the-art microprocessor and contrasted with traditional design flow practices where ideal (i.e., drawn) L/sub gate/ values are employed, leading to a subsequent lack of predictive power. We present a platform for diagnosing and improving OPC quality on gates with specific functionality such as critical gates or matching transistors. Furthermore, with more accurate timing analysis we highlight the necessity of a post-OPC verification embedded design flow, by showing substantial differences in the Si-based timing simulations in terms of significant reordering of speed path criticality and a 36.4% increase in worst-case slack. Extensions of this methodology to multi-layer extraction and timing characterization are also proposed.

Impact of coma on CD control for multiphase PSM designs

Alternating PSM applied selectively to transistor regions on the poly gate mask is one way to achieve smaller gate CDs and tighter CD control. When using multiphase PSMs we have observed, experimentally, a difference between the CDs of isolated lines when the phase shifter is on the right side compared to the left side (we have called this effect the PSM right-left effect). The effect is shown to correlate with lens coma and the magnitude of the effect is also a strong function of defocus. In this paper we present experimental data showing the magnitude of the effect and how it can be minimized by choosing optimum values of numerical aperture (NA) and partial coherence ((sigma) ). The magnitude of the effect within the stepper field is shown to correlate with measured coma values. The sensitivity of the effect to defocus was calculated. Aerial Image simulation was performed and found to predict the experimental behavior to within a factor of two. Variations in PSM design were explored using simulation. In general, the effect is reduced if the PSM layout is symmetrical. By comparing the sensitivity to coma of various PSM designs with the sensitivity of line pair structures on binary masks we were able to determine which designs had acceptable coma sensitivity.

Automatic hotspot classification using pattern-based clustering

This paper proposes a new design check system that works in three steps. First, hotspots such as pinching/bridging are recognized in a product layout based on thorough process simulations. Small layout snippets centered on hotspots are clipped from the layout and similarities between these snippets are calculated by computing their overlapping areas. This is accomplished using an efficient, rectangle-based algorithm. The snippet overlapping areas can be weighted by a function derived from the optical parameters of the lithography process. Second, these hotspots are clustered using a hierarchical clustering algorithm. Finally, each cluster is analyzed in order to identify the common cause of failure for all the hotspots in that cluster, and its representative pattern is fed to a pattern-matching tool for detecting similar hotspots in new design layouts. Thus, the long list of hotspots is reduced to a small number of meaningful clusters and a library of characterized hotspot types is produced. This could lead to automated hotspot corrections that exploit the similarities of hotspots occupying the same cluster. Such an application will be the subject of a future publication.

Clustering and pattern matching for an automatic hotspot classification and detection system

This paper provides details of the implementation of a new design hotspot classification and detection system, and presents results of using the system to detect hotspots in layouts. A large set of hotspot snippets is grouped into a small number of clusters containing geometrically similar hotspots. A fast incremental clustering algorithm is used to perform this task efficiently on very large datasets. Each cluster is analyzed to produce a characterization of a class of hotspots, and a pattern matcher is used to detect hotspots in new design layouts based on the hotspot class descriptions.

Developing DRC Plus Rules through 2D Pattern Extraction and Clustering Techniques

As technology processes continue to shrink and aggressive resolution enhancement technologies (RET) and optical proximity correction (OPC) are applied, standard design rule constraints (DRC) sometimes fails to fully capture the concept of design manufacturability. DRC Plus augments standard DRC by applying fast 2D pattern matching to design layout to identify problematic 2D patterns missed by DRC. DRC Plus offers several advantages over other DFM techniques: it offers a simple pass/no-pass criterion, it is simple to document as part of the design manual, it does not require compute intensive simulations, and it does not require highly-accurate lithographic models. These advantages allow DRC Plus to be inserted early in the design flow, and enforced in conjunction with standard DRC. The creation of DRC Plus rules, however, remains a challenge. Hotspots derived from lithographic simulation may be used to create DRC Plus rules, but the process of translating a hotspot into a pattern is a difficult and manual effort. In this paper, we present an algorithmic methodology to identify hot patterns using lithographic simulation rather than hotspots. First, a complete set of pattern classes, which covers the entire design space of a sample layout, is computed. These pattern classes, by construction, can be directly used as DRC Plus rules. Next, the manufacturability of each pattern class is evaluated as a whole. This results in a quantifiable metric for both design impact and manufacturability, which can be used to select individual pattern classes as DRC Plus rules. Simulation experiment shows that hundreds of rules can be created using this methodology, which is well beyond what is possible by hand. Selective visual inspection shows that algorithmically generated rules are quite reasonable. In addition to producing DRC Plus rules, this methodology also provides a concrete understanding of design style, design variability, and how they affect manufacturability.

Contrast-based assist feature optimization

By defining contrast as the maximum image-log-slope (ILS), we propose a novel method to optimize assist feature sites and locations. We present results that indicate that an ILS optimization at best focus provides enough information to arrive at a solution that improves the depth of focus of the design. Sub-resolution assist features (SRAF) are inserted using a rule-based approach that depends on the equivalent contrast of the original design. Later, an optical rule check (ORC) is performed to identify the regions in which the contrast of the main features is below a certain threshold. After such regions have been properly identified and selected, the neighboring edges are subjected to a sensitivity analysis that returns a contrast matrix which can be later compressed in a global contrast cost function. New positions of the assist feature edges are later evaluated and the assist features are modified accordingly. By following these steps, it is possible to alter: location, width and shape of the assist features in such a way that there is an overall improvement of the main feature contrast. A complete and integrated approach should be able to accept restrictions in the printability of assist features. In order to eliminate errors coming from the cross interactions between the globally optimized assist features and the original design, we incorporate a local clean up procedure that preserves the global validity of the current assist feature rule while improving the local behavior of the original edges. In this fashion, killer defects due to inter-rule dependencies are avoided.

Layout verification and optimization based on flexible design rules

A methodology for layout verification and optimization based on exible design rules is provided. This methodology is based on image parameter determined exible design rules (FDRs), in contrast with restrictive design rules (RDRs), and enables fine-grained optimization of designs in the yield-performance space. Conventional design rules are developed based on experimental data obtained from design, fabrication and measurements of a set of test structures. They are generated at early stage of a process development and used as guidelines for later IC layouts. These design rules (DRs) serve to guarantee a high functional yield of the fabricated design. Since small areas are preferred in integrated circuit designs due to their corresponding high speed and lower cost, most design rules focus on minimum resolvable dimensions.

Inverse vs. traditional OPC for the 22nm node

The 22nm node will be patterned with very challenging Resolution Enhancement Techniques (RETs) such as double exposure or double patterning. Even with those extreme RETs, the k1 factor is expected to be less than 0.3. There is some concern in the industry that traditional edge-based simulate-then-move Optical Proximity Correction (OPC) may not be up to the challenges expected at the 22nm node. Previous work presented the advantages of a so-called inverse OPC approach when coupled with extreme RETs or illumination schemes. The smooth mask contours resulting from inverse corrections were shown not to be limited by topological identity, feedback locality, or fragment conformity. In short, inverse OPC can produce practically unconstrained and often non-intuitive mask shapes. The authors will expand this comparison between traditional and inverse OPC to include likely 22nm RETs such as double dipole lithography and double patterning, comparing dimensional control through process window for each OPC method. The impact of mask simplification of the inverse OPC shapes into shapes which can be reliably manufactured will also be explored.

Design-driven metrology: a new paradigm for DFM-enabled process characterization and control: extensibility and limitations

After more than 2 years of development, Design-Driven Metrology (DDM) is now being introduced into production flows for semiconductor manufacturing, with initial applications targeted at 65 nm and below, but also backward-compatible to 90 nm and above nodes. This paper presents the fundamental components of the DDM framework, and the characteristic architectural relationships among these elements. The discussion includes current status and future prospects for this new metrology paradigm, which represents the true enabler for Design For Manufacturability (DFM) flows and applications. At the core of Design-Driven Metrology lies the simple but powerful concept of utilizing physical design layouts, and more specifically (X,Y) coordinates and polygonal shapes, to automate the generation of metrology jobs. Derived from 10 year old practices of Optical Proximity Correction, the adoption of CAD tools for visualization and manipulation of design layouts, in everyday lithography work, has provided the essential infrastructure for metrology automation. The in-depth discussion of data-flow and system architecture is followed by a presentation of key DDM applications, with specific emphasis on CDSEM metrology, ranging from process development and yield optimization to circuit design. The study concludes with an analysis of the extendibility of DDM and derived flows to other metrology areas in semiconductor manufacturing.

Novel methodology for postexposure bake calibration and optimization based on electrical linewidth measurement and process metamodeling

By combining electrical linewidth measurements and neural-network (NN) process metamodeling, lithography simulators can be calibrated in an efficient way. In this work we present a novel methodology for characterizing postexposure bake using a very large experimental data set, so that the calibrated model can be used as a truly predictive tool. The adoption of a special test reticle mask allowed us to collect more than 700 000 critical dimensions CDs from 24 silicon wafers for a matrix of postexposure bake (PEB) time, and temperature conditions. The lithographic patterns included isolated, semidense and dense lines for structures of 0.25, 0.20, 0.175, and 0.15 μm nominal size replicated across the exposure field and across the wafer. As a result of this particular metrology, each measured CD was associated with both topological (position on the wafer and position within the field) and process information (exposure dose, PEB time, and temperature). Database management techniques were implemented in order t...