Noura Benhadjyoussef

Optimized power trace numbers in CPA attacks

Correlation power analysis is the well-known attack against cryptographic modules. An attacker exploits the correlation between the power consumed by a device and the data being processed. In the present paper, we present the experimental procedure of correlation power analysis using three different devices: FPGA, ASIC and a microcontroller. Results show that the power model used to calculate hypothetical power is related to the algorithm and not to the platform and its validity depends statistically on the implementation.

A compact 32-bit AES design for embedded system

Recently, much research has been conducted for security of data transactions on embedded platforms. Advanced Encryption Standard (AES) is considered as one of a candidate algorithm for data encryption/decryption. One important application of this standard is cryptography on smart cards. In this paper we describe a 32-bits architecture developed for Rijndael algorithm to accelerate execution on 32-bits platforms with reduced memory. Using the FPGA device xc5vfx70t-2ff1136-6, a very low-cost implementation of 375 occupied Slices is obtained under 303.364 MHz frequency.

Enhancing a 32-Bit Processor Core with Efficient Cryptographic Instructions

Embedded processor is often expected to achieve a higher security with good performance and economical use of resource. However, the choice regarding the best solution for how cryptographic algorithms are incorporated in processor core is one of the most challenging assignments a designer has to face. This paper presents an inexpensive instruction set extensions (ISE) of efficient cryptographic algorithms on 32-bit processors assuring various types of instruction (public/private key cryptography, random number generator (RNG) and secure hash function (SHF)). These extensions provide hardware instructions that implement a full algorithm in a single instruction. Our enhanced LEON2 SPARC V8 core with cryptographic ISE is implemented using Xilinx XC5VFX70t FPGA device and an ASIC CMOS 40-nm technology. The total area of the resulting chip is about 1.93 mm2 and the estimated power consumption of the chip is 16.3 mW at 10 MHz. Hardware cost and power consumption evaluation are provided for different clock frequencies and the achieved results show that our circuit is able to be arranged in many security constrained devices.

Location and Positioning Systems: Performance and comparison

In the age of automation the ability to navigate persons and devices in indoor/outdoor environments has become important for many applications.

Hardware Implementations of AES Algorithm for 32-bit Embedded System

The performance evaluation of cryptographic algorithms has guided to serious studies of its implementations. The efficiency of these algorithms is improved by applying good design rules adapted to devices and to its resources constraints. In this paper, we present a careful study of three possible designs of the Advanced Encryption Standard (AES) targeting 32-bit embedded system; we examined AES implementations which use arithmetic properties of the AES S-box and structures based on hardware look-up tables. We have analyzed and compared different characteristics like clock frequency, occupancy area, and power consumption of these implementations. The resulting designs are implemented using Xilinx XC5VFX70t FPGA device and an ASIC CMOS 40 nm technology. Our results show that AES implementation based on hardware look-up table shows the lowest power consumption and highest frequency. The AES implementations which use arithmetic properties of the S-box are characterized by the smallest silicon area.