Hassen Mestiri

Performances of the AES design in 0.18μm CMOS technology

The Advanced Encryption Standard (AES) has been studied by designers with the goal to improve its performances in terms of area, power consumption and frequency. In this paper, we present the implementation details of the AES encryption 128-bit, the MixColumns transformation and the SubBytes transformation. The latter can be implemented using a multi-stage PPRM architecture and composite field arithmetic in GF(((22)2)2). In addition, the MixColumns transformation is used in two architectures. The AES algorithm is implemented using 1.8V 0.18μm Complementary Metal Oxide Semiconductor (CMOS) technology. A low power consumption of 24.92 μW at 10 MHz and 23.2 mW at 67 MHz were achieved for the multi-stage PPRM architecture of SubBytes transformation and the AES encryption respectively. Compared to previous works, our AES implementations achieve good performance in term of power consumption.

A high-speed AES design resistant to fault injection attacks

To secure the Advanced Encryption Standard against physical attacks known as fault injection attacks, different countermeasures have been proposed. The AES is used in many embedded systems to provide security. It has become the default choice for security services in numerous applications. However, the natural and malicious injected faults reduce its robustness and may cause private information leakage. In this paper, we study the concurrent fault detection schemes for achieving a reliable AES implementation. We specifically propose a new fault detection scheme based on modification of the AES architecture. For this purpose, the round AES transformation is broken into two parts and a pipeline stage is inserted in between.The proposed scheme is independent of the way the S-Box and the Inv_S-Box are implemented. Hence, it can be used for both the S-Box and the Inv_S-Box using Look-Up Table and those using logic gates based on Galois Fields. Our simulation results show the fault coverage reaches 98.54% for the proposed scheme. Moreover, the proposed and the previously reported fault detection schemes have been implemented on the most recent Xilinx Virtex FPGAs. Their area overhead, the frequency and throughput have been compared and it is shown that the proposed fault detection scheme outperform the previously reported ones.

High Speed FPGA Implementation of Cryptographic KECCAK Hash Function Crypto-Processor

Cryptographic hash functions are at the heart of many information security applications like message authentication codes (MACs), digital signatures and other forms of authentication. One of the me...

Efficient FPGA hardware implementation of secure hash function SHA-256/Blake-256

Since the beginning of study of the Secure Hash function (SHA), it has been thoroughly studied by designers with the goal of reducing the area, frequency, and throughput of the hardware implementation of this cryptosystem. The Secure Hash function algorithm has become the default choice for security services in numerous applications. In this paper, we proposed a new design for the SHA-256 and Blake-256 functions. Moreover, the proposed design has been implemented on Xilinx Virtex-5 FPGA. Its area, frequency and throughput have been compared and it is shown that the proposed design achieve good performance in term of area, frequency and throughput.

An efficient fault detection scheme for the secure hash algorithm SHA-512

To protect the implementation of the standard Secure Hash Algorithm (SHA) against attacks. We have proposed a number of countermeasures. This paper present a proposed new fault detection scheme. It is based on the hybrid redundancy. The simulation results prove that the fault coverage achieves 99.999% for our scheme proposed. Also, our proposed detection scheme has been implemented on Xilinx Virtex-II Pro FPGA. It is fault coverage, area degradation, frequency, throughput and efficiency overhead have been compared and it is shown that the proposed scheme allows a trade-off between the security and the implementation cost of the SHA implementation.

An AOP-Based Fault Injection Environment for Cryptographic SystemC Designs

The increasing complexity of cryptographic devices requires fast simulation environment in order to test their security against fault attacks. SystemC is one promising candidate in Electronic System Level that allows models to reach higher simulation speed. However in order to enable both fault injection and detection inside a SystemC cryptographic models, its code modification is mandatory. Aspect-Oriented Programming (AOP), which is a new programming paradigm, can be used to test the robustness of the cryptographic models without any code modifications. This may replace real cryptanalysis schemes. In this paper, we present a new methodology to simulate the security fault attacks of cryptographic systems at the Electronic System Level. A fault injection/detection environment is proposed to test the resistance of cryptographic SystemC models against fault injection attacks. The fault injection technique into cryptographic SystemC models is performed using weaving faults by AspectC++ as an AOP programming language. We validate our methodology with two scenarios applied to a SystemC Advanced Encryption Standard case study: the first is related to the impact of the AOP on fault detection capabilities, while the second refers to the impact of the AOP on simulation time and size of the executable files. Simulation results show that this methodology can evaluate perfectly the robustness of a cryptographic design against fault injection attacks. They show that the impact of AOP on simulation time is not significant.

Fault Attacks Resistant Architecture for KECCAK Hash Function

The KECCAK cryptographic algorithms widely used in embedded circuits to ensure a high level of security to any systems which require hashing as the integrity checking and random number generation. One of the most efficient cryptanalysis techniques against KECCAK implementation is the fault injection attacks. Until now, only a few fault detection schemes for KECCAK have been presented. In this paper, in order to provide a high level of security against fault attacks, an efficient error detection scheme based on scrambling technique has been proposed. To evaluate the robust of the proposed detection scheme against faults attacks, we perform fault injection simulations and we show that the fault coverage is about 99,996%. We have described the proposed detection scheme and through the Field-Programmable Gate Array analysis, results show that the proposed scheme can be easily implemented with low complexity and can efficiently protect KECCAK against fault attacks. Moreover, the Field-Programmable Gate Array implementation results show that the proposed KECCAK fault detection scheme realises a compromise between implementation cost and KECCAK robustness against fault attacks.

High throughput pipelined hardware implementation of the KECCAK hash function

The cryptographic hash algorithm has been developed by designers with the goal to enhance its performances in terms of frequency, throughput, power consumption and area. The cryptographic hash algorithm is implemented in many embedded systems to ensure security. It is become the default choice to ensure the information integrity in numerous applications. In this paper, we propose a pipelined architecture of the new algorithm SHA-3 (KECCAK). In addition, the proposed KECCAK architecture has been implemented on Xilinx FPGA platform (Virtex-5). Its frequency, efficiency, throughput and area have been compared and discussed. The FPGA implementation results show that the proposed architecture achieves good performance in terms of frequency and throughput.

A reliable fault detection scheme for the AES hardware implementation

Following the decision to choose Rijndael as the successor of Data Encryption Standard (DES), Advanced Encryption Standard (AES) was increasingly used in numerous applications which require confidentiality and the secure exchange of the data. While security is a property increasingly sought for many applications (credit cards, telecommunications …), it becomes necessary to consider physical attacks as a source of faults. For example, fault attacks are used to change the behavior of a system and recover meaningful data remain secret. This technique is called Differential Fault Analysis (DFA). To protect the AES algorithm against attacks by fault injection, several fault detection schemes were proposed, which is based on information, hardware or temporal redundancy. In this paper, we implemented the AES algorithm in the encryption process. Also, we proposed a reliable fault detection scheme for the AES algorithm. Our simulations show that the fault coverage of the proposed scheme for single and multiple random errors achieves 99.998%. Moreover, the fault coverage, area overhead, throughput and frequency degradation of our modified AES architecture are also compared to those of the previously reported fault detection schemes.

A hardware FPGA implementation of fault attack countermeasure

To secure the Advanced Encryption Standard (AES) implementation against fault injection attacks known as differential fault analysis attacks, different fault detection schemes have been proposed. The AES is used in many embedded systems to provide security. It has become the default choice for security services in numerous applications. In this paper, a parity fault detection scheme has been presented in order to secure AES. This scheme based on parity comparison between the correct parity of the round output and the predicted parity according to the processing steps of the AES round. Moreover, we discuss the strengths and the weaknesses of this scheme against the fault attacks. Experimental synthesis results show that the fault coverage reaches 99.86% for the proposed scheme. The proposed fault detection scheme has been implemented on Xilinx Virtex-5 FPGA. Its fault coverage, area overhead, frequency degradation and throughput have been compared and it is shown that the proposed scheme allows a trade-off between the implementation cost and the security of the AES.