Mourad Loulou

Dual band CMOS LNA design with current reuse topology

A new architecture of dual band receiver was introduced; it is able to make simultaneous operations at two different frequency bands. This architecture uses a new dual band low noise amplifier (LNA). A novel high gain and low noise amplifier topology is proposed. This paper presents a general methodology to design a LNA with current reuse topology for the two standards GSM and UMTS at 947.5MHz and 2.14GHz frequencies respectively, A fully integrated dual band LNA was designed using 0.35mum CMOS process. At 947.5MHz, the LNA exhibits a noise figure of 2.3dB, a voltage gain of 28dB, a CP1 of -12dBm. However, the LNA at 2.14GHz features a noise figure of 2.71dB, a voltage gain of 17dB and a CP1 of -4.5dBm. The power consumption is 37.5mW under a power supply voltage of 2.5V

Optimizing second generation current conveyors using particle swarm optimization

This brief paper deals with using the particle swarm optimization metaheuristic for optimally sizing CMOS positive second generation current conveyors (CCII+). Both static and dynamic performances are improved. Pareto front is generated while minimizing parasitic X-port input resistance RX and maximizing current high cut off frequency fci. The translinear implementation in CMOS technology is presented. Boundaries of the generated Pareto boarder are 400 Omega and 2 GHz for RX and fci respectively. SPICE simulation results are presented to validate obtained sizing.

Comparison between PSO and ACO techniques for analog circuit performance optimization

This paper presents a comparison between swarm intelligence (SI) techniques; namely Particle Swarm Optimization and Ant Colony Optimization, to solve analog circuit sizing problems. Performances in terms of optimum quality and computing time of both algorithms are checked via two applications that consist of optimizing performances of a CMOS second generation current conveyor (CCII), and an operational amplifier (Op-Amp).

Low power SC CMFB folded cascode OTA optimization

This paper describes a design of a switched capacitor common mode feedback (SC CMFB) folded cascode operational transconductance amplifier for low power and high-speed sigma-delta modulators. An algorithmic driven methodology is developed ending to the optimal transistor geometries. Using a 0.35 mum CMOS process, the OTA circuit has been designed to achieve 82.94 dB DC gain, 526 MHz unity-gain frequency, 560 V/mus slew rate with 1.8 V power supply voltage and a power consumption of only 1.19 mW. The simulated OTA circuit has been applied in a SC integrator to illustrate the versatility of the circuit.

Designing VFs by applying genetic algorithms from nullator-based descriptions

An automatic method is proposed to design CMOS compatible voltage followers (VFs) by applying genetic algorithms. It is described how an automatic system can deals with huge search spaces to design practical VFs by performing evolutionary operations from nullator-based descriptions. The proposed method consists of three main steps: generation of the small-signal circuitry, addition of biases, and sizing by using standard CMOS technology of 0.35 mum. Furthermore, it is described how to synthesize VFs by codifying the three main steps into three kinds of genes, and how to select small-signal, biased, and sized topologies to generate potential solutions. Finally, several applications are discussed along with the evolution of VFs to design current conveyors.

A radio frequency CMOS current controlled oscillator based on a new low parasitic resistance CCII

In this paper we present a design of a current controlled oscillator in 0.35pm CMOS process. Owing to their high degree of controllability, the translinear second generation current conveyer is used as a basic block for our oscillator. Thus, the first step in our design was to improve static and dynamic behaviour of second generation current conveyors. The translinear implementation in CMOS technology was first studied. Then a considerable improvement of the parasitic series resistance on port X is done by proposing a new structure. A reduction of RX by nearly a factor of 10 is observed leading to a notable improvement of the frequency behaviour of the proposed oscillator. As an application example, a current controlled oscillator covering [IOOMHz600MHzI frequency range is proposed. Pspice simulation results are performed using CMOS 0.35 pm process of AMs.

A wideband CMOS LNA design for WiMAX applications

In this paper we present the design of a low noise amplifier for WiMAX (802.16 a) standard with AMS 0.35 mum CMOS process. This LNA is designed to cover the frequency range for licensed and unlicensed bands of the WiMAX 2.3 GHz-5.9 GHz. The proposed amplifier achieve a wide band input and output matching with S11 and S22 lower than -10 dB, a flat gain of 13 db and a noise figure between 3dB for all the band and from the upper to the higher frequencies. The presented wide band LNA employs a Chebychev filter for input matching and an inductive shunt feedback for output matching with a bias current of 25 mA and a supply voltage of 2.5 V.

Synthesis of CCIIs and Design of Simulated CCII Based Floating Inductances

It is presented the synthesis of second generation current conveyors (CCIIs) and their use to design simulated floating inductances. The CCIIs are synthesized by combining the connection of current mirrors to optimized voltage followers. Designed non-ideal simulated inductances are used to design a current-mode low-pass fifth order Chebyshev filter and a tunable biband filter. SPICE simulation results are provided to show performances of these filters.

System level design of radio frequency receiver for IEEE 802.16 standard

This paper presents a system level design of radio frequency receiver supporting WiMAX mobile standard. Based on direct conversion receiver, the distribution of the total radio system specifications to the individual receiver components is discussed. System level design techniques and theoretical calculation are developed. Simulation results and system simulation level are introduced for noise figure (NF), gain and linearity (third order intercept point, IIP3). Specifications obtained from the received budget can indicate that the noise and the linearity depend on the gain performance of the corresponding circuit blocks. The receiver achieves a total gain of 23 dB and an IIP3 of -7.8 dBm for low gain mode. It provides up to 68 dB gain, 6.5 dB noise figure and -16 dBm IIP3 for high gain mode.

A power management system for energy harvesting and wireless sensor networks application based on a novel charge pump circuit

ABSTRACT Energy Harvesting circuits are developed as an alternative solution to supply energy to autonomous sensor nodes in Wireless Sensor Networks. In this context, this paper presents a micro-power management system for multi energy sources based on a novel design of charge pump circuit to allow the total autonomy of self-powered sensors. This work proposes a low-voltage and high performance charge pump (CP) suitable for implementation in standard complementary metal oxide semiconductor (CMOS) technologies. The CP design was implemented using Cadence Virtuoso with AMS 0.35μm CMOS technology parameters. Its active area is 0.112 mm2. Consistent results were obtained between the measured findings of the chip testing and the simulation results. The circuit can operate with an 800 mV supply and generate a boosted output voltage of 2.835 V with 1 MHz as frequency.