Nozad Karim

Improving electromagnetic compatibility performance of packages and SiP modules using a conformal shielding solution

High-speed digital and wireless devices radiate unintentional electromagnetic noise, which can affect the normal operation of other devices within the same system, causing intra-system electromagnetic interference (EMI) problems, or contribute to the total radiated EMI from the system, resulting in potential system-level EMI issues. PCB and system level shielding may alleviate the system-level EMI between wireless PCB board and the outside environment, but seldom prevent the intra-system EMI within the shielding enclosure. Package and System in Package (SiP) level shielding is desirable to shield the unintended radiation and protect the other circuits on board. Traditionally an external metal lid is employed to isolate the radiation from an IC, but the package cost and the size penalty due to the solder pads for shield attachment make the solution unattractive. In this paper, a new shielding technology for IC packages based on metal spray coating (conformal shielding) is presented. By spraying a conductive material on the sides of the package, a very thin metal layer is constructed around the top and four sides of a package. This very thin sprayed metal layer adds zero penalty to the package size and works similar to a solid metal shielding with very good shielding effectiveness; hence, it is suitable for wireless infrastructure, tele-communications, and high-speed digital applications.

Electrical characterization of wafer level fan-out (WLFO) using film substrate for low cost millimeter wave application

In this paper, development of wafer level fan-out (WLFO) technology using ajinomoto build-up film (ABF) substrate with laser ablation process is introduced for low cost and high electrical performance for millimeter wave application. Wafer level fan-out (WLFO) technology using ABF substrate can enhance routing density and provide smaller form factor with lower parasitic elements than flip-chip chip scale packages (FCCSP). Moreover, short electrical paths from die out to package out can be realized with WLFO, and the low-k ABF material provides good electrical properties for high frequency areas. In this paper, the process of WLFO using ABF substrate with laser drilling is explained and electrical parasitic elements are compared between FCCSP and WLFO using 3D simulation tools. In addition, electrical characterization of coplanar waveguide (CPW) structure and interconnection models from die I/O pad to balls using 3D EM simulation are conducted to estimate effectiveness on millimeter wave range. Actual measurements of CPW structures are also presented.

Enhancing overall system functionality and performance with the right packaging solutions

Printed circuit boards (PCBs) are the essential parts to assemble modern electronic circuits. The PCB design and development process has a direct impact on the system cost and time to market. On average, companies report that PCB represents 31% of the overall product cost. Todays electronic circuits and PCB designs are extremely complex. Multi-level mistakes are inevitable during the design and development stages. Cost reduction pressure is also limiting the designers in achieving their goals by reducing a few layers from their PCB stackup or adjusting and tweaking their designs. A paradigm shift in PCB design is underway through partitioning and modularizing the system and circuits to reduce PCB size and complexity, shortens design to market time, and simplifies the overall supply chain. In order to develop a superior product to fulfill a desired functions, good balance needs to be achieved among competing factors such as performance, cost, form factors, manufacturability, design, system flexibility, and supply chain management (Fig 1). A wireless system is usually comprised of several subsystems performing different functions. For example, a typical handset system includes baseband, transceivers, main and diversity FEM, memories, power management, power amplifiers, antenna switch, duplexer filter, etc. In this day and age, system integration is mandatory in order for end use products to offer superior and competitive products Compared to an SoC solution, system level integration at the packaging level may provide benefits such as cost effectiveness, flexibility, and a shorter development cycle. A concurrent development methodology between device and package design will definitely help the industry to understand the nature of system integration on a package.

Electromagnetic Shielding for RF and Microwave Packages

Antennas and electromagnetic radiation helped mankind to invent radio, TV, GPS, wireless communication, and many other advanced and convenient technologies that are taken for granted in daily life. Just for a moment, imagine the world without radiation phenomena, a world without antennas and wireless communication. It would be a world without cellphones, TVs, radios, radar and satellite communication to assist in navigating the sky and oceans, a world in the 1800s. Intentional radiation is necessary to make mobile communication possible; however, unintentional radiation is an obstacle to wireless and wired communications, destructive to electronic systems, and harmful to health.

New electrical design verification approach for 2.5D/3D package signal and power integrity

A 2.5D/3D multi die interposer with TSV (Through Silicon Via) allows massive wide parallel busses between memory and logics devices, improves speed, and significantly reduces power consumption. The TSV and silicon interposer are amongst the most promising technologies that offer the greatest vertical interconnects density. This new establishment will change the semiconductor industry paradigm for many years to come. 2.5D/3D technology introduces a new degree of electrical design complexity which is unfamiliar to many existing electrical design methodologies and EDA tools. A new electrical verification methodology must be developed with consideration to the micro level (TSV and interposer structures) and macro/system level simulation. At the Micro level, modeling of TSV is challenging due to its dependency on the material properties of the medium surrounding it and its impact on the signal losses/attenuation, capacitance effects, and the coupling among the vertical interconnects. At the Macro level, new electrical characteristics of the system need to be closely coupled with the thermal and mechanical tolerances of the entire 2.5D/3D packaging structure in order for its ultra wideband data exchange between logic chip and memory chips. TSV placement on logic and memory chips must be carefully placed during the chip design placement stage in order to avoid unnecessary electromagnetic coupling and faulty logic latching. Traditional separate signal and power integrity analysis methodologies are no longer sufficient due to the close proximity of the power and signal distribution network. In order to accurately predict the performance of 2.5D/3D packages, a new design paradigm shift is needed to toggle 2.5D/3D system performance optimization. New design and modeling approaches along with new breeds of computational electromagnetic EDA tools, are paramount to predicting the performance of 2.5D/3D packages.