David Jon Hiner

Multi-die chip on wafer thermo-compression bonding using non-conductive film

Advanced chip on wafer (CoW) assembly has emerged as a key assembly technology for enabling advanced silicon nodes and complex integration. Traditional assembly methods for chip attach have proven capable in this approach, but suffer in the area of fillet design rules. Non-conductive films have been in development as a replacement to the liquid pre-applied underfill materials used in fine pitch copper pillar assembly; however implementation has been slowed by unfavorable cost of ownership and low throughput. Results from recent development have proven the feasibility of a multi-die (gang) bond chip on wafer assembly process. Key assembly steps have been validated and major issues have been mitigated through optimization of materials and process parameters. A scale up phase of development has been initiated which targets the bonding of 8 die (4 units) in a chip on wafer format. The results of this scale up will help move the industry toward a process that can deliver advanced assembly design rules at a cost competitive position when compared to incumbent technologies.

SLIM (TM), High Density Wafer Level Fan-Out Package Development with Submicron RDL

A novel HD-FO package platform was introduced with a hybrid RDL structure. An HD-FO package with hybrid RDL could enables higher routing density and multi die construction in a planner configuration. The 1-µm and submicron RDL wafers were fabricated at a foundry and then the essential parts of the inorganic RDL were integrated with Amkors internal organic RDL process making a hybrid structure. Also, the vertical interconnection on a hybrid RDL made 3-dimentional package construction. Key processes including via reveal, top die attach, and vertical package stacking were successfully demonstrated. Technical challenges in HDFO package development was discussed as well as the reliability performance results both in the package and at the board level.