Giuseppe Selli

Progress in representation and validation of physics-based via models

Vias in printed circuit boards and chip packages are known to have significant detrimental impact on signal and power integrity in high-speed communication systems. Recently, concise equivalent circuit models for vias in multilayer configurations have been explored by the authors. The models accurately reflect the important physical properties of vias, since the topology utilized has a one-to-one correlation to the geometrical structure and the dimensions of the via. In this paper, the proposed physics-based via models are extended to include the interaction between two signal vias and a signal via plus a reference (ground) via. The models were then compared to experimental data obtained from several structures laid out on a 16-layer printed circuit board. The measurements performed using a 4-port vector network analyzer and the high performance recessed probe launching technique evidenced good correlation to 20 GHz and beyond.

SPICE model libraries for via transitions

A procedure of building SPICE models for signal via transitions between printed circuit board layers is presented in this paper. The method of extracting parameters of SPICE models from full-wave simulation tool is demonstrated. Then the validity of SPICE models is studied by comparing the solution from SPICE model with that from the full-wave simulation.

Analysis of noise coupling result from overlapping power areas within power delivery networks

Large area fills or entire planes constitute the backbone of the power delivery network in multi-layer printed circuit boards (PCBs). The overlapping of power areas at different voltages, though, may cause coupling among them. Full wave methods can be used to model these types of structures, and the coupling effect can be accurately analyzed by means of the finite element method (FEM), finite difference time domain (FDTD) and others. However, full wave methods are usually time consuming. In this paper, a cavity model approach is proposed to analyze the noise coupling among plane pairs in multi-layer configurations. The cavity model has analytical expressions for the impedance (Z) matrix associated with ports defined on regularly-shaped planar circuits and it is computationally efficient. The combination of such an approach with the segmentation method allows the extension of the analysis to irregularly shaped and multi-layer structures. A multi-layer PCB with three power planes is analyzed in this article by means of the proposed cavity model approach as well as a full wave FEM method. A comparison between the simulation results obtained with the two different methods is finally provided. Keywords-PDN; cavity model; power bus; overlapping power area; segmentation method; multilayer PCB

Power integrity investigation of BGA footprints by means of the segmentation method

The engineering of the power delivery network is becoming a fundamental issue in the design of high speed digital systems on PCBs. In fact, providing the required power to the different ICs at the specified noise-free voltage levels allows a correct functioning of the overall PCB systems. More over, the ongoing trend of replacing active devices with peripherally located I/O and PWR/GND pins with areally located I/O and PWR/GND pins (BGA packaged) increases the complexity of the models, when power delivery issues need to be studied in a larger contest, such as the overall PCBs. The employment of the powerful, but simple, concept of the segmentation method allows investigation of the power delivery network of the PCB systems in two fundamental stages. During the first stage, a small cut out of the board corresponding to the BGA footprint is modelled with a 3D full wave simulation tool. During the second stage the equivalent impedance network representation corresponding to this cut out is combined, by means of the segmentation method, with larger pieces of a board, whose network representations can be extracted from the closed form expression of the cavity model approach

Validation of equivalent circuits extracted from S-parameter data for eye-pattern evaluation

S-parameter circuit model extraction is usually characterized by a trade off between accuracy and complexity. Trading one feature for another may or may not affect the goodness of the reconstructed S-parameter data, which are obtained from frequency domain simulations of the models extracted. However, the ultimate test for the validity of these equivalent circuit representations should be left to eye-diagram simulations, which provide useful insights, from an SI point of view, about the degradation of the signal, as it travels through the system. Physics based simplification procedures can be used to tune the models and achieve less complexity, whereas the comparisons of the eye-diagrams may help to quantify the goodness of all these circuits extracted. In fact, the most accurate model is not necessary the best to be used.

The importance of using time domain to analyze the effect of decoupling capacitor performance on printed circuit boards

This paper demonstrates the importance of using the time domain to properly analyze decoupling capacitor performance on printed circuit boards as well as ASIC packages, etc. Frequency domain analysis is too limited unless the phase information is used along with the magnitude information. The time domain analysis combines the magnitude and phase information to allow a more accurate analysis of decoupling capacitor distance, decoupling capacitor value, and the effects of connection inductance. The impact of connection inductance is extremely important and it needs to be included in any decoupling capacitor analysis, since this inductance can easily overshadow low plane impedance (by buried capacitance, etc) and make the Power Distribution Network (PDN) ineffective.

Validation of circuit extraction procedure by means of frequency and time domain measurement

Aim of this paper is the validation in both frequency and time domain of the procedure to extract fully H-Spice compatible equivalent circuits of structures on printed circuit boards. The procedure is initiated by standard measurement of scattering parameters between 40 MHz to 20 GH. After the extraction of the equivalent circuit, the computed scattering parameters are compared with those measured. The same equivalent circuit is also used for transient analysis in order to compare TDR measurement and eye-pattern to a pseudo-random bit sequence with those coming from the simulations