Nur Ahmadi

Performance comparison of denoising methods for heart sound signal

This paper presents the performance analysis and comparison of three denosing methods for heart sound signal based on wavelet transform (WT), total variation (TV), and empirical mode decomposition (EMD). Extensive simulations are performed using normal and abnormal heart sound data and the performance is evaluated in terms of signal-to-noise ratio (SNR), root mean square error (RMSE), and percent root mean square difference (PRD). The simulation results show that EMD based denosing method outperforms two other methods.

An optimal architecture of BCH decoder

An optimal architecture for decoding BCH code is presented in this paper. This design uses a new architecture for syndrome computation to avoid multiplication operation, a Modified Direct Solution Algorithm to reduce the time and area consumption, an inverse error locator polynomial to avoid inverse operation in Chien Search, a new architecture for Chien Search and Error Correction using Finite Field Multiplier (FFM) called power FFM and constant FFM, and a manipulation bit method to reduce the number of XOR gates.

Automatic segmentation and detection of heart sound components S1, S2, S3 and S4

In this paper, we propose an automatic segmentation and detection of heart sound components (S1, S2, S3 and S4) which incorporates Empirical Mode Decomposition (EMD) denoising, autocorrelation-based cardiac cycle calculation, Shannon energy envelope extraction, first derivative peak and boundary detection, and real peak selection using Herons formula. The proposed method is evaluated on synthetic data corrupted by white Gaussian noise. The simulation results show that the proposed method is able to segment and identify the heart sound component correctly from normal and abnormal heart sound data.

Design and implementation of visible light communication system using pulse width modulation

Visible Light Communication (VLC) is a relatively new technology which could potentially be complementary to the existing radio frequency communication system. VLC allows lamp or other kinds of light source not only used as illumination, but also as a data transmission at the same time. Single carrier modulation technique is suitable to be applied on VLC that does not require high-speed data transfer. In this paper, we proposed a visible light communication scheme using pulse width modulation (PWM) technique in transmitting data for running text application. To evaluate the PWM accuracy, experiments were conducted based on different parameters such as PWM frequency, transmitter-receiver distance, and the receivers angle of view. Furthermore, we also measured the point-to-point communication system performance which resulted in 920 bps data transfer rate and 10-4 bit error rate (BER) without affecting the lighting function.

VLC physical layer design based on Pulse Position Modulation (PPM) for stable illumination

Visible Light Communication (VLC) is promising new technology to be applied in the lighting system infrastructure. This communication function should not interfere with the existing lighting system. In order to prevent from this interference, the utilized modulation scheme should have a limited dynamic range to avoid flickering and dimming effect. We propose Pulse Position Modulation (PPM) technique in our VLC system due to its very minimum dynamic range feature. This paper describes the design and analysis of VLC physical layer using PPM scheme to obtain a stable illumination. The design of physical layer consists of analog front end (AFE) circuit and the data processing which is implemented in microcontroller and FPGA. Based on the test results of our VLC system using low cost photo detector, the system is able to provide stable illumination while reaching the maximum data transfer rate of 20 kbps.

Hardware implementation of montgomery modular multiplication algorithm using iterative architecture

Modular multiplication is an integral part of RSA cryptosystems and its performance heavily determines the performance of the encryption hardware. This paper provides a hardware implementation of Montgomerys modular multiplication algorithm using iterative architecture. The propsed design is implemented in Verilog HDL and simulated functionally using ModelSim Altera 10.1E. The synthesis is performed using Altera Quartus II 9.1 with target FPGA board Altera DE2-70. The proposed design consumes 17540 logic elements with 15480 LUT and takes 2048 clock cycles to perform multiplication process. Based on trade-off parameter AT2 measure, the proposed design offers the best performance among other designs.

FPGA implementation of CORDIC algorithms for sine and cosine generator

Trigonometric-related calculations which are widely found in a broad range of applications can be performed by using COordinate Rotation DIgital Computer (CORDIC) algorithm. CORDIC is often utilized in the absence of hardware multiplier since this algorithm requires only addition, subtraction, bit shifting, and lookup table. This paper provides an implementation of conventional CORDIC algorithm with pipelined architecture and Virtually Scaling-Free Adaptive (VSFA) CORDIC. All designs are implemented in Verilog and synthesized by using Altera Quartus II with FPGA DE2 as target board. The pipelined CORDIC consumes 1,103 logic element, 33.32 ns latency, and 420.17 MHz maximum frequency, while VSFA CORDIC utilizes 2,109 logic element, 34.96 ns latency, and 343.29 MHz maximum frequency. Both designs are used to generate sine and cosine wave between -π and π which result in maximum error of 8.095 ×2-13 for pipelined CORDIC and 9.183 × 2-13 for VSFA CORDIC. Based on performance comparison in term of area multiplied by delay (A × T), our pipelined CORDIC is superior among other designs.

A pipelined CORDIC architecture and its implementation in all-digital FM modulator-demodulator

COordinate Rotation DIgital Computer (CORDIC), is an algorithm that is used to perform trigonometric-related calculations. CORDIC is often utilized in the absence of hardware multiplier since this algorithm requires only addition, subtraction, bit shifting, and lookup table. This paper provides an implementation of CORDIC algorithm using pipelined architecture. The pipelined CORDIC is then used in an all-digital FM modulator-demodulator. All designs are implemented in Verilog and synthesized by using Altera Quartus software with DE2-70 FPGA target board. The proposed design consumes 1,103 logic element, latency 33.32 ns, and maximum frequency 420.17 MHz. The overall system including FM modulator-demodulator utilizes 3,911 logic elements, latency 233.33 ns, and maximum frequency 60 MHz.

FPGA implementation of modified serial montgomery modular multiplication for 2048-bit RSA cryptosystems

RSA (Rivest, Shamir, Adleman) is one of the most widely used cryptographic algorithms worldwide to perform data encryption and decryption. An essential step in RSA computation lies on its modular multiplication which is relatively expensive and time consuming to be implemented in hardware. This paper proposes two modular multiplication architectures based on modified serial montgomery algorithm for 2048-bit RSA. By limiting the integer modulo that has sequence of A094358, a very simple and fast modular multiplication hardware can be developed. The first archictecture which incorporates 2048-bit adders performes better in term of latency (19010 Logic Cells, 2048 clock cycles or 0.0022 s), while the second architecture utilizing multiple smaller 128-bit adders offers less area consumption (8926 Logic Cells, 36864 clock cycles or 0.0031 s). An area multiplied with squared latency (AT2) can be used as trade-off parameter for choosing the most suitable design for certain need. For prototyping purpose, we have successfully synthesized and implemented our proposed designs written in VHDL using Altera Quartus II with Cyclone II EP2C70F896C6 FPGA as a target board.

CORDIC and Taylor based FPGA music synthesizer

Trigonometric functions of sine and cosine play an important role in a wide variety of applications. COordinate Rotation Digital Computer (CORDIC) and Taylor expansion algorithms are commonly used to calculate those functions. This paper presents the architecture of both CORDIC and Taylor algorithms and their implementation for music synthesizer application. All design modules are written in Verilog HDL and simulated using ModelSim tool. The proposed designs are synthesized using Altera Quartus II software and successfully implemented in Altera DE2 FPGA board. The proposed CORDIC design consumes 1750 area and 222.47 MHz maximum frequency, while the proposed Taylor design utilizes 870 area and 94.73 MHz maximum frequency. Based on AT analysis, CORDIC design performs better than Taylor design.