Amy Hamidah Salman

Performance comparison of denoising methods for heart sound signal

This paper presents the performance analysis and comparison of three denosing methods for heart sound signal based on wavelet transform (WT), total variation (TV), and empirical mode decomposition (EMD). Extensive simulations are performed using normal and abnormal heart sound data and the performance is evaluated in terms of signal-to-noise ratio (SNR), root mean square error (RMSE), and percent root mean square difference (PRD). The simulation results show that EMD based denosing method outperforms two other methods.

Automatic segmentation and detection of heart sound components S1, S2, S3 and S4

In this paper, we propose an automatic segmentation and detection of heart sound components (S1, S2, S3 and S4) which incorporates Empirical Mode Decomposition (EMD) denoising, autocorrelation-based cardiac cycle calculation, Shannon energy envelope extraction, first derivative peak and boundary detection, and real peak selection using Herons formula. The proposed method is evaluated on synthetic data corrupted by white Gaussian noise. The simulation results show that the proposed method is able to segment and identify the heart sound component correctly from normal and abnormal heart sound data.

Visible light communication system for wearable patient monitoring device

A visible light communication (VLC) system design for wearable patient monitoring device is proposed in this paper. This system consists of two devices, patient and coordinator devices. It is two-ways communication scheme. The downlink communication uses VLC, while the uplink uses infrared. It can help the doctor to monitor the patients condition. Moreover, VLC technology is considered to be safer and more comfortable to use. The device uses analog front-end (AFE) and processing module that includes software as the middleware layer. This software comprises MAC and PHY layers. MAC layer manages any kind of packet and transmission to PHY layer. Meanwhile, PHY layer is responsible as driver of transceiver (transmitter and receiver), error correction and data packet. Results of evaluation show the potential of the proposed system to be implemented in real life healthcare systems.

Review of digital heart sound classification methods via Artificial Neural Networks

In this paper we discuss three types of Artificial Neural Networks which are commonly used in classification process. Those are Kohonens Self-Organizing Map (SOM), Incremental Self-Organizing Map (ISOM), and Multi-Layer Perception Back Propagation (MLP-BP).

SOC design and FPGA implementation of Digital TV receiver

This paper proposes a System-on-chip (SoC) Architecture Design for real-time Digital TV receiver. The SoC includes RF interface, a Host Processor, a Physical Layer and Ethernet interface. The Physical Layer itself consists of Baseband Processing modules based on DVB-T standard which includes 2048-point FFT/IFFT, Channel Decoder, Synchronizer, Equalizer, Demodulator, etc. The SoC utilizes a 32-bit RISC based processor acting as the Host Processor. Both Processor and Physical layer works on 32 MHz clock cycle to ensure low power consumption. A real-time OS based on eCos is also used for controlling the Physical Layer and interfaces in a real-time basis. The system is implemented using FPGA and has been verified capable of receiving a realtime video transmitted by a standard digital TV transmitter/modulator.

Establishment of Wi-Fi Display session between source and sink device in wireless Android screencasting

Wireless technology has been rapidly developing. Wi-Fi Alliance several years ago presented Wi-Fi Direct, a new feature that makes it possible to connect devices using ad-hoc network. Since then this technology has been developed and now comes Wi-Fi Display (WFD). This technology is utilized to implement the system of wireless Android screencasting. This system will cast/mirror the Android screen to other screen using a wireless connection. To establish the WFD session, there are respectively two processes: The Wi-Fi Direct connection establishment and the negotiation process.

Design and implementation of DCBOTA in Delta-Sigma ADC for communication system

In this paper, we present the design and implementation of high-resolution and low-power Operational Transconductance Amplifier (OTA) which can be utilized in Delta-Sigma ADC for GSM communication system. The designed OTA is called Dynamic Comparator-Based Operational Transconductance Amplifier (DCBOTA). The DCBOTA is implemented in layout and is tested with SPICE-based computer simulation. The test shows that the designed DCBOTA is functional and has good performance. Furthermore, the overall Delta-Sigma ADC is also implemented in layout, but the design process is not shown in this paper. The test shows that the Delta-Sigma ADC based on DCBOTA requires lower power than other Delta-Sigma ADCs for GSM communication system.

MASH Delta Sigma ADC layout for dual mode GSM & WLAN application

Analog to Digital Converter (ADC) is a component which transforms analog signals into digital signals. This paper focused on designing oversampling ADC with Delta-Sigma modulator which will be used in GSM and WLAN baseband communication system. The proposed Delta-Sigma ADC is divided into three main parts, which are pre-processing, modulator, and post-processing modules. Pre-processing module has important role in converting the input signal, which has continuous value continuous time characteristic, to be discrete time continuous value signal. Modulator is needed to process the signal from pre-processing module to be pulse signal, while post-processing module will convert the pulse signal into digital signal. The pre-processing part is implemented by sample and hold circuit. Modulator is designed using cascaded modulator topology - a number of four modulators are cascaded with MASH 2-1-1-1 configuration. Each modulators block has feedback topology with 1-bit quantizer and works in discrete time domain. Hence, ADC system is implemented in layout of 180 nm technology, which consists of OTA, capacitor, comparator, and digital logic circuit. Decimation Filter of 5-stage CIC filter is needed for the implementation of postprocessing module.

Design and implementation of SAR ADC for Time-to-Digital Converter application

Time-to-Digital Converter (TDC) has been widely used in several applications such as time-of-flight measurement, high-energy physics experiment and bio-medical imaging. There are two generations of TDC implementation. In this paper we propose a SAR ADC design which has been adapted as a building block of the first generation of TDC. Design and simulation performed with 180nm CMOS technology, Our design could obtained +0.125 / -0.75 DNL, + 0.75 / -1 INL, 844.2uW power consumption and 10-bit output.

DVB-T synchronizer architecture design and implementation

This paper presents the design of synchronizer hardware for DVB-T receiver. The main function of synchronizer is to detect and compensate the time offset and frequency offset which happen during transmission as well as frame start detection. Proposed synchronizer utilizes cyclic prefix of OFDM signals. The design includes computational bit precision modeling, architecture design, register-transfer-level (RTL) codes implementation, and final synthesis into FPGA. The synthesis result shows that the synchronizer can satisfy the required specification of at least more than 40MHz clock speed, i.e., specifically 55MHz clock setup.