Trio Adiono

Reduced stall MIPS architecture using pre-fetching accelerator

This paper describes the design of a MIPS architecture with a small number of stall. Stall frequently happens in pipeline architecture which results in larger clock cycles. In this paper we significantly reduced stall by introducing pre-fetching unit. This unit reduces stall by concurrently reading three instructions and check their possibility of stall. If stall is detected, this unit then changes the sequence of executed instructions. Furthermore, we also employ forwarding and memory hazard detection units to further reduce stall. In order to increase the processor functionality and performances, especially for RSA security application, we include two new instructions 32-bit mult and mod. The design has been successfully implemented in FPGA DE2 Board (Terasic) and standard call CMOS 0.13u. As system verification, we successfully execute bubble sort program and RSA encryption. The system implementation reach the maximum frequency of 714 MHz.

High mobility data pilot based channel estimation for downlink OFDMA system based on IEEE 802.16e standard

High mobility communication systems need suitable channel estimation to cope high frequency selectivity channel effect. In this paper we propose data pilot based channel estimation in downlink OFDMA for IEEE 802.16e standard (mobile WiMAX). The mobile WiMAX channel estimation can be done by exploiting pilot from preamble, in this paper we obtain channel transfer function by exploiting pilot at symbol data with two dimensional interpolation scheme. Based on our simulation, it can be shown that the proposed method have better performance compare with preamble based channel estimation method. Afterwards we compare linear interpolation and MMSE interpolation for proposed channel estimation method. The symbol error rate for QPSK and 64 QAM system is presented by means of simulation.

Face focus coding under H.263+ video coding standard

In this paper, we present a new method to enhance image quality at face region of head and shoulder type image sequence and to shorten processing latency to achieve synchronization between lip movement and voice (lip sync). The new method can significantly improve image quality at face region and reduce frame skip operation during high movement image coding. Improvement is done by allocating more bits budget to the face region, where the centre of perceptual interest point usually located. Total number of bits of dynamically change background region is compressed by applying temporal filter to suppress background noise. We design a new fast rate control based on non-zero coefficient evaluation to shorten compression latency. The experimental result shows the increment of face regions PSNR by around 2 dB, the decreasing of skipping operation around 60 frames during encoding of 382 frames of highly movement video sequence and the advantage of having a very small compression latency around 3 frames which can resolve the lips sync problem.

Wireless protocol design for smart home on mesh wireless sensor network

This paper proposes a formulation scheme for communication data protocol at the application layer that can adapt to heterogeneous smart objects which may arise in the case of Smart Home application. Mesh-based design WSN is an attempt to realize the Smart Home concept, where DigiMesh topology is chosen as the basic topology in experimental setup of WSN. Mobile device is the main object as monitoring and controlling devices. Mapping the address and description of each bit in a predetermined protocol, then can be implemented in various condition. With the dynamic characteristics of the design of this protocol, the power cost can be reduced to a minimum. Protocol design has been successfully tested in scenario of monitoring and controlling function. Application of the CheckSum method is also reported to help in the detection error of data packet.

A pipelined double-issue MIPS based processor architecture

This paper explains a new design of a high speed MIPS (Microprocessor without Interlocked Pipelined Stages) based processor with significant improvements on instruction-level parallelism (ILP) and stall reduction to zero. These improvements are accomplished by utilizing four-stage pipelining, multiple-issue technique, and a Branch Target Buffer. The processor functionality has been verified on Altera DE2 FPGA board to run bubble-sort program. The maximum clock frequency achieved for the design on Altera DE2 FPGA board is 63.27 MHz.

Patient monitoring using Visible Light uplink data transmission

Patient health monitoring technology presents great potential for future healthcare applications and Radio Frequency (RF) communication is the most popular medium for its implementation. This paper presents a static indoor patient monitoring scheme using uplink Visible Light Communication (VLC) suitable for hospital environments. VLC is considered instead of RF communication because of health concerns regarding continuous RF exposure to patients for health monitoring. The proposed scheme is designed for transmitting uplink patient data using VLC through On-Off Keying (OOK) modulation. Experiments were conducted with several body-sensors data transmitted using predefined headers. The experiment results show that the proposed VLC based patient monitoring scheme can offer accurate monitoring data transmission with minimal interference with the help of space diversity.

Low complexity partial sampled MMSE channel estimation for downlink OFDMA IEEE 802.16e system

Channel estimation is one of key problems in IEEE 802.16e Orthogonal Frequency Division Multiplexing Access (OFDMA) downlink system. Minimum Mean Square Error (MMSE) channel estimation has been known as a superior performance channel estimation. However, this algorithm has high computational complexity. In this paper, we present low complexity partial-sampled MMSE channel estimation for compromising between complexity and performance. We reduced MMSE channel estimation complexity by partially sampling the MMSE weight matrix. The simulation results show that the bit error rate (BER) performance significantly improved over the least square channel estimation and has comparable BER performance with MMSE channel estimation at low SNR. Depending the sixze of sampling, significant decrease 57 % to 64 % in computational complexity can be achieved.

64-point fast efficient FFT architecture using Radix-23 single path delay feedback

Here we present a new design of a 64-point Fast Fourier Transform circuit. The design is derived from Radix-23 algorithm and implemented using Single Path Delay Feedback architecture. This approach ensures high memory and multiplier utilizations. The 64-Point FFT is realized by decomposing into two-dimensional structure of 8-point FFTs. Each of this FFT is re-decomposed into 4-point and 2-point FFTs. This decomposition reduces the number of non-trivial twiddle factor into just one. Thus we only need one complex multiplier for the design. The complex multiplier is realized using modified Booth (radix-4) encoding algorithm to achieve faster computational speed. The validity and efficiency of the proposed circuit has been thoroughly verified by functional simulation, timing simulation, and FPGA implementation. The proposed design has been successfully synthesized using Synopsys with TSMC 0.18µ technology. The core area is 0.47 mm2. The power consumption is 29.7 mW. The time delay is 6 ns. The circuit computes one serial-to-serial data in 116 clock cycles. Thus our design has 3 advantages: small area, low power consumption, and fast computation.

Camera object tracking system

This paper presents a pan and tilt camera system that can follow a predefined object that move freely under a specific constraint. We use a stepping motor that work in a half step mode, provides a minimum of 0.9 degree movement, but it is adequate as a pan and tilt actuator system for the specified usage. A Kalman filter is used to estimate the object motion in the block matching process due to disorder changes due to the image being close to other views for several frames. A Motorola DSP 56002 is used as a controller processor for the actuator driver and the frame grabber Visionetics International installed in the Pentium 100. The sampling time is 3 frame/second.

Preamble structure-based timing synchronization for IEEE 802.16e

This paper proposes timing synchronization for IEEE 802.16e OFDMA downlink. The proposed scheme utilizes the conjugate symmetry property of preamble structure. Therefore, prior knowledge of actual transmitted preamble type is not required. Considering hardware complexity, this paper proposes a new single correlation function for 114 different structures of preamble in 802.16e OFDMA. As a consequence, this method eliminates need to cross correlation with all possible preamble. Comparing to conventional method, the correlation produces very high sharp peak that easy the determination of the start of preamble result. The simulation results show that the proposed synchronization method is suitable for multipath environment. Under ITU-B pedestrian channel, our proposed method can correctly identify all preambles at SNR larger than −2dB, and under ITU-A vehicular channel, our proposed method can achieve reasonable performance at SNR larger than −1dB.