O. Petre

On-chip tap-delay measurements for a digital delay-line used in high-speed inter-chip data communications

During the last few years, new synchronization techniques to send data between ICs at increasingly high data-rates have been developed. Some of them rely on digital delay lines. The timing accuracy of the delay lines is crucial for good functionality of the synchronization mechanism. This paper presents a strategy to measure the tap-delays of a digital delay-line, using the well-known oscillation technique. The occurring measurement error for the presented technique has been calculated. Towards the end of the paper, a new delay-line scheme is shown. The tap-delay, measurement becomes much more accurate for this delay-line than for a standard delay-line.

Increasing the fault coverage in multiple clock domain systems by using on-line testing of synchronizers

As a result of shrinking minimum feature size, IC clock frequencies are increasing and it is no longer possible, nor desired, to stick to a single clock domain. Multiple-clock domain design will no longer be an isolated design style. This new trend in the industry, referred to as future standard by some companies, poses a lot of test problems due to special modules utilized at the interface between clock domains. These modules are called synchronizers. This paper will present an implementation of the on-line concept on two different synchronizers and it will calculate the probability to detect any stuck-at fault.