R.J.W.T. Tangelder

Integration of the Scan-Test Method into an Architecture Specific Core-Test Approach

In this paper a concept is proposed to combine a bus-transfer based test approach (AMBA) with the well-known scan-test technique. This novel approach combines the advantages of modularity and core reuse (AMBA) with the benefits of high fault coverages and short time-to-market cycles (scan). The consequences with respect to test hardware implementation and tool flow are discussed.

Practical implementation of defect-oriented testing for a mixed-signal class-D amplifier

This paper describes the flow of defect-oriented testing from beginning to end, based on the industrial test development for a commercial mixed-signal class-D amplifier. A software tool called DOTSS (Defect-Oriented Test Simulation System) was used to perform the fault simulations. The greatest benefit of using defect-oriented testing turns out to be that it gives more insight in the underlying fault mechanisms. This information can be used to generate complementary tests or to take design-for-testability measures to achieve a high fault coverage.

Jitter and decision-level noise separation in A/D converters

Gaussian aperture jitter leads to a reduced SNR of A/D converters. Also other noise sources, faults and nonlinearities affect the digital output signal. A measurement setup for a new off-chip diagnosis method, which systematically separates the jitter-induced errors from the errors caused by these other factors, is described. Deterministic errors are removed via a subtracting technique. High-level ADC simulations and measurements have been carried out to determine relations between the size of the jitter or decision-level noise and the remaining random errors. By carrying out two tests at two different input frequencies and using the simulation results, errors induced by decision-level noise can be removed.

Off-Chip Diagnosis of Aperture Jitter in Full-Flash Analog-to-Digital Converters

Gaussian aperture jitter leads to a reduction in the Signal-to-Noise-Ratio of A/D converters. Other noise sources, faults and nonlinearities also effect the digital output signal. A new off-chip diagnosis method, which systematically separates the jitter-induced errors from the errors caused by these other factors, is described. Deterministic errors are removed via a subtraction technique. High-level ADC simulations have been carried out to determine relations between the size of the jitter or decision-level noise and the remaining random errors. By carrying out two tests at two different input frequencies and using the simulation results, errors induced by decision-level noise can be removed.

Smart sensor system application: an integrated compass

A fully integrable electronic compass has been designed based on the pulse position method, using micro-machined fluxgate magnetic sensors. The compass has been designed to have an accuracy of one degree. The analogue and digital circuitry in the system fit on a single Sea-of-Gates array of 200 k transistors. Together with the sensors it will be combined on a single MCM.

MISMATCH: a basis for semi-automatic functional mixed-signal test-pattern generation

This paper describes a tool which assists the designer in the rapid generation of functional tests for mixed-signal circuits down to the actual test-signals for the tester. The tool is based on manipulating design data, making use of macro-based test libraries and tester resources provided by the test engineer, and computer-based interaction with the designer.

Computer-aided test flow in core-based design

This paper copes with the test-pattern generation and fault coverage determination in the core based design. The basic core-test strategy that one has to apply in the core-based design is stated in this work. A Computer-Aided Test (CAT) flow is proposed resulting in accurate fault coverage of embedded cores. The CAT now is applied to a few cores within the Philips Core Test Pilot IC project.

An implementation for test-time reduction in VLIW transport-triggered architectures

In this paper the implementation of the test strategy in a so-called Very Long Instruction Word Transport Triggered Architecture (VLIW-TTA) is discussed. The complete test strategy is derived referring to the results of test synthesis, carried out in the early phase of the design. It takes the area/throughput parameters into account. The test strategy, exploiting the regularity and modularity of the VLIW-TTA structure, remains general for an arbitrary application and instantiation of the TTA processor and is based on the partial scan approach along with the functional test. The test-time analysis, in order to justify our approach and show the superiority over the classical full-scan, has been performed. The results of our strategy are shown in a few examples at the end of the paper.

Mixed-Signal Testing at the ASIC Design Course at Twente University

At our faculty the students have to follow an extensive (mixed-signal) ASIC design course in the third year of the program. In [1] we have presented an overview of the whole course, but in the meanwhile we have extended the mixed-signal test part of this ASIC design course considerably. In our course the students have to design and test a so-called dial-memo IC (see Figure 1).

Integrated Design and Test of Mixed-Signal Circuits

In this paper, the integration of design and test flows for mixed-signal circuits is discussed. The aim is to decrease test generation and debugging costs and time-to-market for the analogue blocks in mixed-signal circuits. A tool developed in order to automate the data sharing between design and test environments is described and the functionality of this tool is explained. The generation of a test plan consists of the selection of the separate test functions and addition of commands for control signal generation and tester routing. The usage of design data for each of these functions is explained and the tool is evaluated in the design and testing of a mixed-signal demonstrator circuit. Results from this experience are discussed.