Octavian Buiu

Interface Defects in HfO2, LaSiOx, and Gd2O3 High-k/Metal-Gate Structures on Silicon

In this work, we present experimental results examining the energy distribution of the relatively high (> 1 X 10(11) cm(-2)) electrically active interface defects which are commonly observed in high-dielectric-constant (high-k) metal-insulator-silicon systems during high-k process development. This paper extends previous studies on the Si(100)/SiOx/HfO2 system to include a comparative analysis of the density and energy distribution of interface defects for HfO2, lanthanum silicate (LaSiOx), and Gd2O3 thin films on (100) orientation silicon formed by a range of deposition techniques. The analysis of the interface defect density across the energy gap, for samples which experience no H-2/N-2 annealing following the gate stack formation, reveals a peak density (similar to 2 X 10(12) cm(-2) eV(-1) to similar to 1 X 10(13) cm(-2) eV(-1)) at 0.83-0.92 eV above the silicon valence bandedge for the HfO2, LaSiOx, and Gd2O3 thin films on Si (100). The characteristic peak in the interface state density (0.83-0.92 eV) is obtained for samples where no interface silicon oxide layer is observed from transmission electron microscopy. Analysis suggests silicon dangling bond (P-bo) centers as the common origin for the dominant interface defects for the various Si(100)/SiOx/high-k/metal gate systems. The results of forming gas (H-2/N-2) annealing over the temperature range 350-555 degrees C are presented and indicate interface state density reduction, as expected for silicon dangling bond centers. The technological relevance of the results is discussed. (c) 2007 The Electrochemical Society.

Oxidation of silicon nitride films in an oxygen plasma

The fabrication of oxynitrides using low thermal budget process technology is a key component in the production of advanced devices. This work focuses on the use of plasma anodization of low-pressure chemical vapor deposition (LPCVD) silicon nitride films to produce silicon oxynitride films, which are characterized structurally and electrically. The oxynitride dielectric films have a three layer structure, with “SiO2”-like layers at the surface and near the interface, and a “Si3N4”-like layer between them. Hence, nitrogen atoms are replaced by oxygen atoms at the surface of the film and near the Si/dielectric interface. The conductivity of the silicon nitride film was found to be higher than the silicon oxynitride film, whereas the conductivity of the oxynitride and, therefore, its trapping characteristics are more temperature dependent. Furthermore, the activation energy required to release an electron from a trap in the silicon oxynitride film (0.218 eV) is 1.7× that of the silicon nitride film (0.130 e...

Shallow junctions on pillar sidewalls for sub-100-nm vertical MOSFETs

A simple process for the fabrication of shallow drain junctions on pillar sidewalls in sub-100-nm vertical MOSFETs is described. The key feature of this process is the creation of a polysilicon spacer around the perimeter of the pillar to connect the channel to a polysilicon drain contact. The depth of the junction on the pillar sidewall is primarily determined by the thickness of the polysilicon spacer. This process is CMOS compatible and, hence, facilitates the integration of a sub-100-nm vertical MOSFET in a planar CMOS technology using mature lithography. The fabricated transistors have a subthreshold slope of 95 mV/dec (at VDS=1 V) and a drain-induced barrier lowering of 0.12 V

SiGe HBTs on bonded SOI incorporating buried silicide layers

A technology is described for fabricating SiGe heterojunction bipolar transistors (HBTs) on wafer-bonded silicon-on-insulator (SOI) substrates that incorporate buried tungsten silicide layers for collector resistance reduction or buried groundplanes for crosstalk suppression. The physical structure of the devices is characterized using cross section transmission electron microscopy, and the electrical properties of the buried tungsten silicide layer are characterized using sheet resistance measurements as a function of bond temperature. Possible contamination issues associated with the buried tungsten silicide layer are investigated by measuring the collector/base reverse diode tics. A resistivity of 50 /spl mu//spl Omega/cm is obtained for the buried silicide layer for a bond anneal of 120 min at 1000/spl deg/C. Collector/base reverse diode tics show a voltage dependence of approximately V/sup 1/2/, indicating that the leakage current is due to Shockley-Read-Hall generation in the depletion region. Fitting of the current-voltage tics gives a generation lifetime of 90 ns, which is as expected for the collector doping of 7 /spl times/ 10/sup 17/ cm/sup -3/. These results indicate that the buried tungsten silicide layer does not have a serious impact on junction leakage.

Surface leakage current related failure of power silicon devices operated at high junction temperature

Operation of power silicon diodes above the maximum permissible specified junction temperature can lead to device catastrophic failure that is usually caused by an electrical short-circuit located at the junction peripheral surface. It is shown that a noticeable surface leakage reverse current component found in the available commercial devices may cause I-V reverse characteristic instability through thermal runaway and finally device failure. Suitable junction passivation can reduce further the surface component so that reliable operation above 200 C junction temperature to be possible at least for standard recovery PN junction devices.

On the Design of a Low Power Compact Spiking Neuron Cell Based on Charge-Coupled Synapses

A charge-coupled silicon synapse with a floating diffusion output is proposed as the basis for a new electronic, spiking neuron cell. The synapse is formed by a two-stage charge transfer device with the weight function stored in a floating gate over the first stage. The output of the synapses feeds into the multi-gate inputs of a MOSFET which themselves capacitively couple onto a common floating gate. This MOSFET provides a summing action and so acts as a point neuron. Thermal generation within the synaptic device, causes relaxation of the signals and this can be tailored to provide realistic postsynaptic potential (PSP) dependencies. Simulation results show that this architecture can generate a PSP that effectively mimics the spiking behaviour of real synapses. The cell is highly compact and intrinsically low power and so offers the potential for biologically plausible spiking neural networks (SNNs) in hardware.

High-k-oxide/silicon interfaces characterized by capacitance frequency spectroscopy

Electron capture into insulator/silicon interface states is investigated for high-k dielectrics of Gd2O3 prepared by MBE and ALD, and for HfO2 prepared by reactive sputtering, by measuring the frequency dependence of MOS capacitance. The capture cross sections are found to be thermally activated and to increase steeply with the energy depth of the interface electron states. The methodology adopted is considered useful for increasing the understanding of high-k-oxide/silicon interfaces.

Tuneable electrical properties of hafnium aluminate gate dielectrics deposited by metal organic chemical vapour deposition.

Abstract Hafnium aluminate (HfAlO) high-k films deposited by Metal Organic Chemical Vapour Deposition (MOCVD) with various Al concentrations were investigated. The results of electrical measurements show the feasibility of adjusting the relative dielectric constant of the layers in a wide range (9–16), when the aluminium concentration varies between 4% and 38%. The minimum leakage current occurs for Al concentrations up to 9%. The thinner films show Poole–Frenkel-like conduction at low field and Fowler–Nordheim-like conduction at moderate/high field, even at higher concentrations of Al into the film, while thicker films show a higher hysteresis due to an increased number of slow trapping centres in the film.

Electrical characteristics of present-day manufactured power semiconductor pn junctions and the I-V characteristic theory

Experimental characteristics derived from available samples at this time of silicon commercial devices, manufactured by leading companies in the field are presented. It is shown that experimental evidence for a dominant surface current component may also he in good agreement with the predictions of the current voltage characteristic theory where the junction surface leakage current is ignored. The semiconductor power devices have electrical characteristics under the influence of a surface leakage component. This is the primary reverse current component for standard recovery junctions and may be the secondary component for fast recovery junctions. The existence of a surface leakage component has impact on the performance of power devices at high junction temperature.

Surface acoustic wave CO 2 sensing with polymer-amino carbon nanotube composites

The synthesis of two new types of nanocomposite matrices, the first based on polyallylamine (PAA) and aminocarbon nanotubes, the second on polyethyleneimine (PEI) and aminocarbon nanotubes, are reported. The surface acoustic wave (SAW) sensors, coated with the two selected nanocomposites, showed good sensitivities when varying the CO2 concentrations in the range (500-5000) ppm. The sensor sensitivity is larger when using polyethyleneimine aminocarbon nanotubes than in the case when only a pure polyethyleneimine layer is considered for coating.