Octavian Cret

An FPGA-specific approach to floating-point accumulation and sum-of-products

This article studies two common situations where the flexibility of FPGAs allows one to design application-specific floating-point operators which are more efficient and more accurate than those offered by processors and GPUs. First, for applications involving the addition of a large number of floating-point values, an ad-hoc accumulator is proposed. By tailoring its parameters to the numerical requirements of the application, it can be made arbitrarily accurate, at an area cost comparable to that of a standard floating-point adder, and at a higher frequency. The second example is the sum-of-product operation, which is the building block of matrix computations. A novel architecture is proposed that feeds the previous accumulator out of a floating-point multiplier whose rounding logic has been removed, again improving the area/accuracy tradeoff. These architectures are implemented within the FloPoCo generator, freely available under the LGPL.

Automatic Test Data Generation for Software Path Testing Using Evolutionary Algorithms

Software testing is a very expensive and time consuming process. Test methods which generate test data based on the programs internal structure are intensively used. This paper presents a comparison between three important Evolutionary Algorithms used for automatic test data generation, a technique that forces the execution of a desired path of the program called target path. Two new approaches, based on Particle Swarm Optimization and Simulated Annealing algorithms, used in conjunction with the approximation level and branch distance metrics, are compared with Genetic Algorithms for generating test data. The results obtained based on the proposed approaches suggest that evolutionary testing strategies are very well suited to generate test data which cover a target path inside a software program.

Real-Time Testing of True Random Number Generators Through Dynamic Reconfiguration

This paper presents the hardware implementation of the widely known NIST Statistical Test Suite – a battery of statistical tests for pseudorandom number generators (PRNGs) and true random number generators (TRNGs) – in a single Xilinx FPGA chip, using dynamic partial reconfiguration. The design offers a basic framework for easy integration of any additional randomness evaluation tests as well. Due to the integration of both the TRNG and the tests suite in a single FPGA chip, our solution offers new opportunities in the area of random number generation and testing, greatly reducing the time between the generation and the validation of the generated sequences of random bits.

Practical Issues in Implementing TRNGs in FPGAs Based on the Ring Oscillator Sampling Method

Field programmable gate arrays (FPGAs) are an increasingly popular choice of platform for the implementation of cryptographic systems. For all such systems, random numbers are essential. One of the most well-known methods for producing true random number sequences in FPGAs is based on the phenomenon of jitter and built upon ring oscillators. This paper describes how to overcome the placement sensitivity caused by the different physical properties of the logic elements, thus extending the portability of TRNGs on various FPGA boards. Our design offers an easy implementation, but in the same time maintains the good quality and high generation throughput of random numbers.

A Prototype for the Remote Monitoring of Water Parameters

Continuous real-time water parameters monitoring is a necessity in the context of contemporary water resources management. There is an important research direction towards the development of monitoring systems, which make use of wireless sensor networks for water parameters acquisition. In this paper, we present our on-going work and preliminary findings on the development of a water parameters monitoring system. We propose a prototype for monitoring water parameters that uses wireless sensor networks for data acquisition. Moreover, we describe a usage scenario for the proposed prototype that is aimed at detecting accidental pollution in rivers.

Highly Efficient True Random Number Generator in FPGA Devices Using Phase-Locked Loops

This paper presents a new type of True Random Number Generator (TRNG) based on jitter and metastability implemented in the latest family of Xilinx FPGA devices. The source of randomness is the Phase-Locked Loop (PLL) that is present on such devices, which exhibits jitter due to one of the analog component in it. For extracting the random bits the design uses the same clock as the PLLs input clock. The quality of the TRNG is given by the entropy source used, the single-chip implementation, and the high throughput (of the order of several megabits per second) obtained. It is confirmed by the fact that all the classical test batteries (NIST, DIEHARD, Test U01 and ENT) yielded very good results when ran on the generated random bits stream.

Implementing Modular FFTs in FPGAs -- A Basic Block for Lattice-Based Cryptography

Modular FFTs are essential primitives in many application fields. This paper explores the improvements that can be obtained through the use of an FPGA device for implementing modular FFTs. Although the architectural study presented in this paper is generic, the implementation has been particularized for the field of Lattice-based Cryptography, which uses modular FFTs. We present three main FPGA implementation variants for a modular FFT and perform a thorough scalability analysis for the parameters set proposed in the literature so far for the SWIFFT(X) hash function (an FFT of order 64 on Z257).

FPGA based TRNG using automatic calibration

This paper presents a new method to improve the quality of True Random Number Generators implemented on Field Programmable Gate Arrays. Traditionally implementations require an exact manual calibration to achieve the best performance. In this paper we are suggesting a method which uses modern clocking features to perform automatic calibration. This feature also enable the efficient use of some jitter sources previously unavailable to designers. The present design also uses one of these sources, the jitter available on the clock lines. The implementation has the advantage of a relatively high throughput in a small size. The quality of the generated stream is also high, passing multiple test suites. The implementation is also provided as a calibrating framework which can be easily reused for other designs.

CREC: a novel reconfigurable computing design methodology

The main research done in the field of reconfigurable computing was oriented towards applications involving low granularity operations and high intrinsic parallelism. CREC is an original, low-cost general-purpose reconfigurable computer whose architecture is generated through a hardware/software codesign process. The main idea of the CREC system is to generate the best-suited hardware architecture for the execution of each software application. The CREC parallel compiler parses the source code and generates the hardware architecture, based on multiple execution units. The hardware architecture is described in VHDL code, generated by a program. Finally, CREC is implemented in an FPGA device. The great flexibility offered by the general-purpose CREC system makes it interesting for a wide class of applications that mainly involve high intrinsic parallelism, but also any other kinds of computations.

Water Parameters Monitoring on a Cyberwater Platform

With the raise of global concerns about climate changes and pollution in general, water monitoring became a major topic of interest in geospatial applications. There are a significant number of parameters that need to be monitored in a watershed, and varieties of sensors are used for this purpose. In modern sensor networks, sensors are not just simple data collectors, but also actuators that need complex programming. This paper presents a monitoring system for water parameters, based on a wireless sensors network (WSN) and the process of measuring several water quality parameters, aiming to detect pollutants. The experimental results, obtained using the Cyber water platform for monitoring pollution on rivers, confirm the quality of the approach.