Radu Tudoran

An FPGA-specific approach to floating-point accumulation and sum-of-products

This article studies two common situations where the flexibility of FPGAs allows one to design application-specific floating-point operators which are more efficient and more accurate than those offered by processors and GPUs. First, for applications involving the addition of a large number of floating-point values, an ad-hoc accumulator is proposed. By tailoring its parameters to the numerical requirements of the application, it can be made arbitrarily accurate, at an area cost comparable to that of a standard floating-point adder, and at a higher frequency. The second example is the sum-of-product operation, which is the building block of matrix computations. A novel architecture is proposed that feeds the previous accumulator out of a floating-point multiplier whose rounding logic has been removed, again improving the area/accuracy tradeoff. These architectures are implemented within the FloPoCo generator, freely available under the LGPL.

Multipliers for floating-point double precision and beyond on FPGAs

The implementation of high-precision floating-point applications on reconfigurable hardware requires large multipliers. Full multipliers are the core of floating-point multipliers. Truncated multipliers, trading resources for a well-controlled accuracy degradation, are useful building blocks in situations where a full multiplier is not needed. This work studies the automated generation of such multipliers using the embedded multipliers and adders present in the DSP blocks of current FPGAs. The optimization of such multipliers is expressed as a tiling problem, where a tile represents a hardware multiplier, and super-tiles represent combinations of several hardware multipliers and adders, making efficient use of the DSP internal resources. This tiling technique is shown to adapt to full or truncated multipliers. It addresses arbitrary precisions including single, double but also the quadruple precision introduced by the IEEE-754-2008 standard and currently unsupported by processor hardware. An open-source implementation is provided in the FloPoCo project.

Software Random Number Generation Based on Race Conditions

The paper presents a new software strategy for generating true random numbers, by creating several threads and letting them compete unsynchronized for a shared variable, whose value is read-modified-updated by each thread repeatedly. The generated sequence of random numbers consists of the final values of the shared variable. Our strategy is based on the functionality of the operating systems thread scheduler. Different values of the shared variable are obtained because the concurrent threads are preempted at different moments in their execution. We identified some software and hardware factors that make the scheduler generate context switches at unpredictable moments: execution environment, cache misses, the instruction execution pipeline and the imprecision of the hardware clock used to generate timer interrupts. We implemented the strategy on x86 architecture running Linux operating system. The random number sequences obtained pass over 90% of the NIST tests.

FPGA-Based Acceleration of the Computations Involved in Transcranial Magnetic Stimulation

In the last years the interest for magnetic stimulation of the human nervous tissue has increased, because this technique has proved its utility and applicability both as a diagnostic and as a treatment instrument. Research in this domain is aimed at eliminating some disadvantages of the technique: the lack of focalization of the stimulated human body region and the reduced efficiency of the energetic transfer from the stimulating coil to the tissue. Designing better stimulation coils is so far a trial-and-error process, relying on very compute-intensive simulations. In software, such a simulation has a very high running time (several hours for complicated geometries of the coils). This paper proposes and demonstrates an FPGA-based hardware implementation of this simulation, which reduces the computation time by 2-3 orders of magnitude. Thanks to this powerful tool, some significant improvements in the design of the coils have already been obtained.

Exploiting Crosstalk Effects in FPGAs for Generating True Random Numbers

This paper presents a new method for implementing TRNGs in FPGA devices, which relies on filling a region or the whole FPGA chip close to its maximal capacity and exploiting the interconnection network as intensely as possible. This way, there are strong chances for the design to exhibit a nondeterministic behavior. Our first design is a computationally intensive core that generates 64-bit numbers, accumulated into a fixed-point accumulator. The bits that exhibit the maximal entropy are then post-processed using the XOR-based bias reduction method. We prove that the resulting TRNG provides high quality random numbers. An explanation of the underlying phenomenon is proposed, based on electromagnetic interferences inside the chip and crosstalk effects. A systematic method for developing TRNG designs based on this approach is proposed and an improved TRNG architecture is then presented.