Oded Katz

High-power high-linearity SiGe based E-BAND transceiver chipset for broadband communication

Fully integrated chipset at E-band frequencies in a superhetrodyne architecture covering the lower 71-76GHz and upper 81-86GHz bands were designed and fabricated in 0.13μm SiGe technology. The receiver chips include an image-reject low-noise amplifier (LNA), RF-to-IF mixer, variable gain IF amplifier, quadrature IF-to-baseband de-modulators, tunable baseband filter, phase-locked loop (PLL), and frequency multiplier by four (quadrupler). The receiver chips achieve maximum gain of 65dB, 6dB noise figure, better than -10 dBm IIP3, with more than 65 dB dynamic range, and consumes 600 mW. The transmitter chips include a power amplifier, image-reject driver, IF-to-RF up-converting mixer, variable gain IF amplifier, quadrature baseband-to-IF modulator, PLL, and frequency quadrupler. It achieves output power at P1dB of 17.5 to 18.5 dBm, Psat of 20.5 to 21.5 dBm, an analog controlled dynamic range of 30 dB and consumes 1.75 W.

A fully integrated SiGe E-BAND transceiver chipset for broadband point-to-point communication

Fully integrated chipset at E-band frequencies in a superhetrodyne architecture covering the lower 71-76 GHz and upper 81-86 GHz bands were designed and fabricated in 0.13%m SiGe technology. The receiver chips include an image-reject low-noise amplifier (LNA), RF-to-IF mixer, variable gain IF amplifier, quadrature IF-to-baseband de-modulators, tunable baseband filter, phase-locked loop (PLL), and frequency multiplier by four (quadrupler). The receiver chips achieve 60dB gain, 8.5 dB noise figure, -30 dBm IIP3, and consumes 600 mW. The transmitter chips include a power amplifier, image-reject driver, IF-to-RF up-converting mixer, variable gain IF amplifier, quadrature baseband-to-IF modulator, PLL, and frequency multiplier by four (quadrupler). It achieves output power P1dB of 0 to 11 dBm, Psat of 3.3 to 14 dBm, and consumes 850 mW.

An active up conversion mixer covering the entire 71–86GHz Eband range in SiGe Technology

An IF to RF up-conversion mixer for the entire E-BAND 71-76 GHz and 81-86 GHz frequency range was designed and fabricated in IBM 0.12 μm SiGe technology. The Mixer comprises of a double balanced Gilbert-cell with a degeneration inductor in the amplifying stage for increased linearity. The mixer exhibits conversion gain higher than -2 dB, output compression point above -7 dBm, and LO leakage less than -30 dB. The core mixer area is 0.37 mm2 and consumes 140 mW from a 2.7 V power supply.

A high suppression frequency tripler for 60-GHz transceivers

A compact frequency tripler designed for 60 GHz transceivers is implemented in 0.13μm SiGe technology. The common emitter class-A frequency tripler uses a transformer based output filter combined with transmission lines to achieve high harmonic suppression. The frequency tripler followed by an amplifier covers a 3dB frequency range between 48 GHz to 58 GHz with a peak output power of 9.5 dBm. Fundamental frequency is suppressed by more than 28 dBc and the 4th harmonic is suppressed by more than 35 dBc between -40°C to 85°C degrees across the frequency band. The tripler design occupies only 390 μm × 495 μm and consumes 62 mW from a 2.7 V supply, the design followed by an amplifier occupies 960 μm × 980 μm raising the DC consumption to 220 mW.

A SiGe E-band transceiver circuits for broadband communication

Two sets of E-band transceiver circuits in a superhetrodyne architecture covering the lower 71–76GHz and upper 81–86GHz bands were designed and fabricated in 0.13μm SiGe technology. The measured upper band transmitter RF gain chain is 30dB with a saturated output power of 15.2dBm. The LNA exhibits more than 15dB gain. A frequency quadrupler was used to generate the LO signal in both transmitter and receiver enabling a single PLL design with reuse of 60GHz intermediate and baseband circuits. The measured value of quadrupler conversion gain is approximately −8dB, to our best knowledge the highest reported value for a SiGe frequency quadrupler. Measurements of fabricated critical circuits in conjunction with modifications performed to proven 60GHz transceiver components enables a complete E-band transceiver circuit solution covering the entire E-band frequency range. The paper will focus on the critical E-band building blocks.

A robust low phase noise K u band VCO with 23.3% tuning range for E-band and V-band backhaul transceivers

This paper presents a Ku band Gm boosted Colpitts VCO designed in IBM 0.13μm SiGe BiCMOS8hp technology for E-Band and V-band backhaul transceivers. The VCO achieves 23.3% tuning range, covering 15.2 - 19.2 GHz while maintaining low phase noise. Measured phase noise at 10 MHz is lower than -133 dBc/Hz at 25°C. The VCO shows robust behaviour to temperature variations, with a measured frequency drift of less than 15 ppm/°C. The power consumption is 51.4mW and calculated FOM is -183.5 dBc/Hz.

High-performance 81–86 GHz transceiver chipset for Point-to-Point communication in SiGe BiCMOS technology

Fully integrated chipset at E-band frequencies in a superhetrodyne architecture covering the 81-86 GHz band was designed and fabricated in 0.13 μm SiGe technology. The receiver chip includes an image-reject low-noise amplifier (LNA), RF-to-IF mixer, variable gain IF amplifier, quadrature IF-to-baseband de-modulators, tunable baseband filter, phase-locked loop (PLL), and frequency multiplier by four (quadrupler). The receiver chip achieves maximum gain of 73 dB, 6 dB noise figure, better than -12 dBm IIP3, with more than 65 dB dynamic range, and consumes 600 mW. The transmitter chip includes a power amplifier (PA), image-reject driver, variable RF attenuators, IF-to-RF upconverting mixer, variable gain IF amplifier, quadrature baseband-to-IF modulator, PLL, and frequency quadrupler. It achieves output power at P1dB of 16.6 dBm, Psat of 18.8 dBm on a single-ended output and consumes 1.8 W.

A low phase noise Ku-band sub-integer frequency synthesizer for E-band transceivers

A Ku band frequency synthesizer is designed and implemented in 0.13 μm SiGe technology as a part of an E-band superhetrodyne transceiver chipset. It provides for RF channels of 71-76 GHz in 62.5 MHz steps, and features a phase rotating pulse injection division region switching sub-integer frequency divider. Output frequency ranges from 15.4 to 16.7 GHz. The measured differential output power is about -6 dBm measured phase noise at 100-kHz 1-MHz and 10 MHz is -84, -111 and -131 dBc/Hz, respectively. Reference spurs are at -44 dBc and sub-integer spurs are at -45 dBc, with power consumption of 166 mW.

A K-band low phase noise and high gain Gm boosted colpitts VCO for 76–81 GHz FMCW radar applications

This paper presents a low phase noise and high gain Gm boosted Colpitts Voltage Controlled Oscillator (VCO) that covers a 9.8% continuous tuning range spanning 18.79 to 20.73 GHz. The tank was modified to facilitate the VCO to maintain low phase noise despite having high gain. Designed and implemented in IBM 0.13μm SiGe BiCMOS8hp technology, the measured phase noise at 10 MHz offset ranges between -140 to -132.5 dBc/Hz throughout the entire tuning range with a maximum gain of 2 GHz/Volt. The VCO is optimized for a 76 to 81 GHz FMCW radar when cascaded with a frequency multiplier by four. The VCO core consumes 29mA from a 2V regulator.

SiGe based Ka-band reflection type phase shifter for integrated phased array transceivers

Phase shifters are key components in phased array systems. A low loss and low loss variations SiGe differential phase shifter for the Ka-band is described. This bidirectional differential reflection type phase shifter (RTPS) design employs a novel diagonal configuration for the coupler and it is controlled by a single voltage node. The measured results show state of the art insertion loss of 5±1 dB, phase tuning range larger than 180 degrees, for a frequency range of 26.5 GHz to 32.8 GHz (21%). At 30 GHz, the phase shifter exhibits insertion loss of 4.8 dB, loss variation of ±0.4 dB, and more than 206 degrees of phase shift range. The RTPS was fabricated in a standard BiCMOS SiGe process and occupies 0.64 mm2 die area.