Benny Sheinman

High-power high-linearity SiGe based E-BAND transceiver chipset for broadband communication

Fully integrated chipset at E-band frequencies in a superhetrodyne architecture covering the lower 71-76GHz and upper 81-86GHz bands were designed and fabricated in 0.13μm SiGe technology. The receiver chips include an image-reject low-noise amplifier (LNA), RF-to-IF mixer, variable gain IF amplifier, quadrature IF-to-baseband de-modulators, tunable baseband filter, phase-locked loop (PLL), and frequency multiplier by four (quadrupler). The receiver chips achieve maximum gain of 65dB, 6dB noise figure, better than -10 dBm IIP3, with more than 65 dB dynamic range, and consumes 600 mW. The transmitter chips include a power amplifier, image-reject driver, IF-to-RF up-converting mixer, variable gain IF amplifier, quadrature baseband-to-IF modulator, PLL, and frequency quadrupler. It achieves output power at P1dB of 17.5 to 18.5 dBm, Psat of 20.5 to 21.5 dBm, an analog controlled dynamic range of 30 dB and consumes 1.75 W.

A fully integrated SiGe E-BAND transceiver chipset for broadband point-to-point communication

Fully integrated chipset at E-band frequencies in a superhetrodyne architecture covering the lower 71-76 GHz and upper 81-86 GHz bands were designed and fabricated in 0.13%m SiGe technology. The receiver chips include an image-reject low-noise amplifier (LNA), RF-to-IF mixer, variable gain IF amplifier, quadrature IF-to-baseband de-modulators, tunable baseband filter, phase-locked loop (PLL), and frequency multiplier by four (quadrupler). The receiver chips achieve 60dB gain, 8.5 dB noise figure, -30 dBm IIP3, and consumes 600 mW. The transmitter chips include a power amplifier, image-reject driver, IF-to-RF up-converting mixer, variable gain IF amplifier, quadrature baseband-to-IF modulator, PLL, and frequency multiplier by four (quadrupler). It achieves output power P1dB of 0 to 11 dBm, Psat of 3.3 to 14 dBm, and consumes 850 mW.

An active up conversion mixer covering the entire 71–86GHz Eband range in SiGe Technology

An IF to RF up-conversion mixer for the entire E-BAND 71-76 GHz and 81-86 GHz frequency range was designed and fabricated in IBM 0.12 μm SiGe technology. The Mixer comprises of a double balanced Gilbert-cell with a degeneration inductor in the amplifying stage for increased linearity. The mixer exhibits conversion gain higher than -2 dB, output compression point above -7 dBm, and LO leakage less than -30 dB. The core mixer area is 0.37 mm2 and consumes 140 mW from a 2.7 V power supply.

A high suppression frequency tripler for 60-GHz transceivers

A compact frequency tripler designed for 60 GHz transceivers is implemented in 0.13μm SiGe technology. The common emitter class-A frequency tripler uses a transformer based output filter combined with transmission lines to achieve high harmonic suppression. The frequency tripler followed by an amplifier covers a 3dB frequency range between 48 GHz to 58 GHz with a peak output power of 9.5 dBm. Fundamental frequency is suppressed by more than 28 dBc and the 4th harmonic is suppressed by more than 35 dBc between -40°C to 85°C degrees across the frequency band. The tripler design occupies only 390 μm × 495 μm and consumes 62 mW from a 2.7 V supply, the design followed by an amplifier occupies 960 μm × 980 μm raising the DC consumption to 220 mW.

A SiGe E-band transceiver circuits for broadband communication

Two sets of E-band transceiver circuits in a superhetrodyne architecture covering the lower 71–76GHz and upper 81–86GHz bands were designed and fabricated in 0.13μm SiGe technology. The measured upper band transmitter RF gain chain is 30dB with a saturated output power of 15.2dBm. The LNA exhibits more than 15dB gain. A frequency quadrupler was used to generate the LO signal in both transmitter and receiver enabling a single PLL design with reuse of 60GHz intermediate and baseband circuits. The measured value of quadrupler conversion gain is approximately −8dB, to our best knowledge the highest reported value for a SiGe frequency quadrupler. Measurements of fabricated critical circuits in conjunction with modifications performed to proven 60GHz transceiver components enables a complete E-band transceiver circuit solution covering the entire E-band frequency range. The paper will focus on the critical E-band building blocks.

Silicon-chip single and coupled coplanar transmission line measurements and model verification up to 50GHz

Silicon technology on-chip single and coupled coplanar transmission lines have been measured on wafer up to 50 GHz. De-embedding was performed using various methods including the L-2L technique [1,2] by measuring two transmission lines of original and double length. A novel approach has been used for the measurement of the coupled structures using conventional two port VNA. Results are investigated both in S-parameter format and in gamma-Zo format, and compared with EM solver and the parametric IBM coplanar T-line device models discussed elsewhere [3,4] which are available in IBM CMOS and SiGe technology design kits. A comparison with RC model shows the limits of RC model validity, in frequency domain.

High-performance 81–86 GHz transceiver chipset for Point-to-Point communication in SiGe BiCMOS technology

Fully integrated chipset at E-band frequencies in a superhetrodyne architecture covering the 81-86 GHz band was designed and fabricated in 0.13 μm SiGe technology. The receiver chip includes an image-reject low-noise amplifier (LNA), RF-to-IF mixer, variable gain IF amplifier, quadrature IF-to-baseband de-modulators, tunable baseband filter, phase-locked loop (PLL), and frequency multiplier by four (quadrupler). The receiver chip achieves maximum gain of 73 dB, 6 dB noise figure, better than -12 dBm IIP3, with more than 65 dB dynamic range, and consumes 600 mW. The transmitter chip includes a power amplifier (PA), image-reject driver, variable RF attenuators, IF-to-RF upconverting mixer, variable gain IF amplifier, quadrature baseband-to-IF modulator, PLL, and frequency quadrupler. It achieves output power at P1dB of 16.6 dBm, Psat of 18.8 dBm on a single-ended output and consumes 1.8 W.

A low phase noise Ku-band sub-integer frequency synthesizer for E-band transceivers

A Ku band frequency synthesizer is designed and implemented in 0.13 μm SiGe technology as a part of an E-band superhetrodyne transceiver chipset. It provides for RF channels of 71-76 GHz in 62.5 MHz steps, and features a phase rotating pulse injection division region switching sub-integer frequency divider. Output frequency ranges from 15.4 to 16.7 GHz. The measured differential output power is about -6 dBm measured phase noise at 100-kHz 1-MHz and 10 MHz is -84, -111 and -131 dBc/Hz, respectively. Reference spurs are at -44 dBc and sub-integer spurs are at -45 dBc, with power consumption of 166 mW.

High conversion gain high suppression SiGe based balanced cascode frequency quadrupler at 60–77GHz

This paper demonstrates a frequency multiplier by four (quadrupler) with a cascade topology that exhibits a high conversion gain and high suppression for the 60–77 GHz. Most of the repotted balanced frequency multiplier at mmWave range are frequency doublers, which means that an additional stage have to be used in order to get higher frequency multiplication factor. An additional stage will come at the expense of chip area, power consumption and will have relatively low conversion gain due to the cascading of to multiplying stages. Typically an additional amplifying and filter will have to be used between the stages. Furthermore, each doubler stage has to be tuned for a different frequency range. Finally, the resulting conversion efficiency will be low, thus forcing us to add additional amplifying stages at the forth harmonic. [1]