Olin L. Hartin

Worst Case Power/Ground Noise Estimation Using an Equivalent Transition Time for Resonance

The nonmonotonic behavior of power/ground noise with respect to the transition time tr is investigated for an inductive power distribution network with a decoupling capacitor. The worst case power/ground noise obtained with fast switching characteristics is shown to be significantly inaccurate. An equivalent transition time that corresponds to resonance is presented to accurately estimate the worst case power/ground noise in the time domain. Furthermore, the sensitivity of the ground noise to the decoupling capacitance Cd and parasitic inductance Lg is evaluated as a function of the transition time. Increasing the decoupling capacitance is shown to efficiently reduce the noise for transition times smaller than twice the LC time constant, tr les 2radic(LgCd). Alternatively, reducing the parasitic inductance Lg is shown to be effective for transition times greater than twice the LC time constant, tr ges 2radic(LgCd). The peak noise occurs when the transition time is approximately equal to twice the LC time constant, tr ap 2radic(LgCd) , referred to as the equivalent transition time for resonance.

Efficient placement of distributed on-chip decoupling capacitors in nanoscale ICs

Decoupling capacitors are widely used to reduce power supply noise. On-chip decoupling capacitors have traditionally been allocated into the white space available on the die based on an unsystematic or ad hoc approach. In this way, large decoupling capacitors are often placed at a significant distance from the current load, compromising the signal integrity of the system. This issue of power delivery cannot be alleviated by simply increasing the size of the on-chip decoupling capacitors. To be effective, the on-chip decoupling capacitors should be placed physically close to the current loads. The area occupied by the on-chip decoupling capacitor, however, is directly proportional to the magnitude of the capacitor. The minimum impedance between the on-chip decoupling capacitor and the current load is therefore fundamentally affected by the magnitude of the capacitor. A distributed on-chip decoupling capacitor network is proposed in this paper. A system of distributed on-chip decoupling capacitors is shown to provide an efficient solution for providing the required on-chip decoupling capacitance under existing technology constraints. In a system of distributed on-chip decoupling capacitors, each capacitor is sized based on the parasitic impedance of the power distribution grid. Various tradeoffs in a system of distributed on-chip decoupling capacitors are also discussed. Related simulation results for typical values of on-chip parasitic resistance are also presented. An analytic solution is shown to provide accurate distributed system. The worst case error is 0.003% as compared to SPICE. Techniques presented in this paper are applicable not only for current technologies, but also provide an efficient placement of the on-chip decoupling capacitors in future technology generations.

Electrothermal Monte Carlo Simulation of GaN HEMTs Including Electron–Electron Interactions

A Monte Carlo device simulator was developed to investigate the electronic transport properties in AlGaN/GaN high-electron mobility transistors (HEMTs). Electron-electron interactions were included using a particle-particle-particle-mesh coupling scheme. Quantum corrections were applied to the heterointerface using the effective potential approach due to Ferry. Thermal effects were also included by coupling the particle-based device simulator self-consistently with an energy balance solver for the acoustic and optical phonons. The electrothermal device simulator was used to observe the temperature profiles across the device. Hot spots or regions of higher temperatures were found along the channel in the gate-drain spacing. Results from electrothermal simulations show self-heating degradation of performance at high source-drain bias. More importantly, the observed nonequilibrium phonon effects may play an important role in determining the thermal distribution in these HEMTs, resulting in reliability issues such as current collapse.

Importance of the Gate-Dependent Polarization Charge on the Operation of GaN HEMTs

We investigate the influence of the gate-voltage dependence of the polarization charge on the electron sheet charge density in the channel and how it reflects on the device transfer and output characteristics in GaN HEMTs. We find that a 10% increase in the polarization charge is needed to match the experimental data when the gate-voltage dependence of the polarization charge is included in the theoretical model. This information is important for calibration in commercial device simulators and for better understanding of the quality of the GaN/AlGaN interface.

Methodology for Efficient Substrate Noise Analysis in Large-Scale Mixed-Signal Circuits

A methodology is proposed to efficiently analyze substrate noise coupled to a sensitive block due to an aggressor digital block in large-scale mixed-signal circuits. The methodology is based on identifying voltage domains on the substrate by exploiting the small spatial voltage differences on the ground distribution network of the aggressor circuit. Specifically, similarly biased regions on the substrate short-circuited by the ground network are determined, and each of these regions is represented by a single equivalent input port to the substrate. The remaining ports within that domain are ignored to reduce the computational complexity of the extraction process. An algorithm with linear time complexity is proposed to merge those substrate contacts exhibiting a voltage difference smaller than a specified value, identifying a voltage domain. An equivalent contact is placed at the geometric mean of the merged contacts, ignoring all of the remaining ports such as the source/drain junctions of the devices. The ground network impedance is updated for each merged contact based on the proposed algorithm to maintain sufficient accuracy of the noise voltage. The substrate with reduced input ports is extracted using an existing extraction tool to analyze the noise at the sense node. As compared to the full extraction of an aggressor circuit, the methodology achieves a reduction of more than four orders of magnitude in the number of extracted substrate resistors with a peak-to-peak error of 24%.

On-Chip Power Noise Reduction Techniques in High Performance SoC-Based Integrated Circuits

Switching digital circuits produce current peaks which result in voltage fluctuations on the power supply lines due to the inductive behavior of on-chip and chip-to-package interconnects. A design technique is described in this paper to lower ground bounce in noise sensitive circuits. An on-chip noise-free ground is added to divert ground noise from the sensitive nodes. An on-chip decoupling capacitor tuned in resonance with the parasitic inductance of the interconnects provide an additional low impedance ground path. Ground bounce reductions of about 68% and 22% are demonstrated for a single frequency and random noise, respectively. The noise reduction is shown to depend linearly on the physical separation between the noisy and noise sensitive blocks. The dependence of ground noise on the impedance of the low noise ground is also discussed. The proposed technique exhibits a strong tolerance to capacitance variations. The efficiency of the noise reduction technique drops by several per cent for a plusmn10% variation in the magnitude of the decoupling capacitor. The proposed technique is shown to be effective for both single frequency and random voltage fluctuations on the ground terminal

Efficient Distributed On-Chip Decoupling Capacitors for Nanoscale ICs

A distributed on-chip decoupling capacitor network is proposed in this paper. A system of distributed on-chip decoupling capacitors is shown to provide an efficient solution for providing the required on-chip decoupling capacitance under existing technology constraints. In a system of distributed on-chip decoupling capacitors, each capacitor is sized based on the parasitic impedance of the power distribution grid. Various tradeoffs in a system of distributed on-chip decoupling capacitors are also discussed. Related simulation results for typical values of on-chip parasitic resistance are also presented. The worst case error is 0.003% as compared to SPICE.

Compact substrate models for efficient noise coupling and signal isolation analysis

Current propagation within a lightly doped substrate is approximated with a half-ellipse to efficiently estimate substrate resistances. As opposed to existing work, the proposed model contains only one fitting parameter. Compact models are also developed to determine the isolation efficiency of several commonly used structures such as a guard ring and triple well. The accuracy of these models is verified by comparing the models with a commercial substrate extraction tool based on a boundary element method. These models are used to compare several isolation structures within an industrial mixed-signal circuit with a lightly doped substrate.

AlGaN/GaN HEMT TCAD simulation and model extraction for RF applications

GaN devices have significant advantages in power density, thermal characteristics, and voltage range over those based on conventional compound semiconductors or Silicon. With GaN, as in other materials systems there are significant advantages in cycle time and strength of design from use of TCAD. Here TCAD simulations of AlGaN/GaN HEMTs are shown to accurately match measured DC and small signal AC data. For large signal RF applications it is necessary to use modeling to extend the application of this TCAD solution. Proprietary models are extracted from TCAD data and demonstrated.

Characterization and thermal analysis of a 48 V GaN HFET device technology for wireless infrastructure applications

This report presents the DC, pulsed I–V, small signal, and large signal characteristics of Freescale’s 48 V GaN HFET technology. Characterization of large signal performance for a 12.6 mm at 48V drain bias shows 89 W output power with an associated power density of 7.1 W/mm, linear gain of 17.5 dB, and a power-added efficiency (PAE) of 62%. Analysis of channel temperature over drain bias shows that the maximum channel temperatures at 28 V and 48 V are 107 °C and 245 °C, respectively during saturated RF operation. Data for RF drift over time on a 16.2 mm device show less than 0.2 dB of RF drift for ≫1000 hrs. of testing. This level of RF performance represents a significant ≫4 dB gain and ≫2 W/mm power density improvement over Freescale’s previously reported GaN HFET technology.