Emre Salman

Exploiting Setup–Hold-Time Interdependence in Static Timing Analysis

A methodology is proposed to exploit the interdependence between setup- and hold-time constraints in static timing analysis (STA). The methodology consists of two phases. The first phase includes the interdependent characterization of sequential cells, resulting in multiple constraint pairs. The second phase includes an efficient algorithm that exploits these multiple pairs in STA. The methodology improves accuracy by removing optimism and reducing unnecessary pessimism. Furthermore, the tradeoff between setup and hold times is exploited to significantly reduce timing violations in STA. These benefits are validated using industrial circuits and tools, exhibiting up to 53% reduction in the number of constraint violations as well as up to 48% reduction in the worst negative slack, which corresponds to a 15% decrease in the clock period

Worst Case Power/Ground Noise Estimation Using an Equivalent Transition Time for Resonance

The nonmonotonic behavior of power/ground noise with respect to the transition time tr is investigated for an inductive power distribution network with a decoupling capacitor. The worst case power/ground noise obtained with fast switching characteristics is shown to be significantly inaccurate. An equivalent transition time that corresponds to resonance is presented to accurately estimate the worst case power/ground noise in the time domain. Furthermore, the sensitivity of the ground noise to the decoupling capacitance Cd and parasitic inductance Lg is evaluated as a function of the transition time. Increasing the decoupling capacitance is shown to efficiently reduce the noise for transition times smaller than twice the LC time constant, tr les 2radic(LgCd). Alternatively, reducing the parasitic inductance Lg is shown to be effective for transition times greater than twice the LC time constant, tr ges 2radic(LgCd). The peak noise occurs when the transition time is approximately equal to twice the LC time constant, tr ap 2radic(LgCd) , referred to as the equivalent transition time for resonance.

Pessimism Reduction In Static Timing Analysis Using Interdependent Setup and Hold Times

A methodology is proposed for interdependent setup time and hold time characterization of sequential circuits. Integrating the methodology into an industrial sign-off static timing analysis tool is described. The proposed methodology prevents optimism and reduces unnecessary pessimism, both of which exist due to independent characterization. Furthermore, the tradeoff between interdependent setup and hold times is exploited to significantly reduce slack violations. These benefits are validated using industrial circuits and tools

Power Distribution in TSV-Based 3-D Processor-Memory Stacks

Three primary techniques for manufacturing through silicon vias (TSVs), via-first, via-middle, and via-last, have been analyzed and compared to distribute power in a 3-D processor-memory system with nine planes. Due to distinct fabrication techniques, these TSV technologies require significantly different design constraints, as investigated in this paper. A valid design space that satisfies the peak power supply noise while minimizing area overhead is identified for each technology. It is demonstrated that the area overhead of a 3-D power distribution network with via-first TSVs is approximately 9% as compared to less than 2% in via-middle and via-last technologies. Despite this drawback, a via-first based power network is typically overdamped and the issue of resonance is alleviated. A via-last based power network, however, exhibits a relatively low damping factor and the peak noise is highly sensitive to the number of TSVs and decoupling capacitance.

Noise coupling due to through silicon vias (TSVs) in 3-D integrated circuits

Three-dimensional (3-D) integration is a promising technology to alleviate the interconnect bottleneck by stacking multiple dies in a monolithic fashion. Both power dissipation and delay can be reduced by utilizing the third dimension where through silicon vias (TSVs) are used for vertical communication. Characteristics of switching noise that couples to a sensitive device due to a TSV are investigated in this paper. A model is developed to evaluate the noise performance of a TSV. Several noise isolation strategies are also discussed. Ignoring noise characteristics during the TSV placement process produces a poor 3-D circuit with high susceptibility to switching noise.

Methodology for Efficient Substrate Noise Analysis in Large-Scale Mixed-Signal Circuits

A methodology is proposed to efficiently analyze substrate noise coupled to a sensitive block due to an aggressor digital block in large-scale mixed-signal circuits. The methodology is based on identifying voltage domains on the substrate by exploiting the small spatial voltage differences on the ground distribution network of the aggressor circuit. Specifically, similarly biased regions on the substrate short-circuited by the ground network are determined, and each of these regions is represented by a single equivalent input port to the substrate. The remaining ports within that domain are ignored to reduce the computational complexity of the extraction process. An algorithm with linear time complexity is proposed to merge those substrate contacts exhibiting a voltage difference smaller than a specified value, identifying a voltage domain. An equivalent contact is placed at the geometric mean of the merged contacts, ignoring all of the remaining ports such as the source/drain junctions of the devices. The ground network impedance is updated for each merged contact based on the proposed algorithm to maintain sufficient accuracy of the noise voltage. The substrate with reduced input ports is extracted using an existing extraction tool to analyze the noise at the sense node. As compared to the full extraction of an aggressor circuit, the methodology achieves a reduction of more than four orders of magnitude in the number of extracted substrate resistors with a peak-to-peak error of 24%.

Shielding Methodologies in the Presence of Power/Ground Noise

Design guidelines for shielding in the presence of power/ground (P/G) noise are presented in this paper. The effect of P/G noise on crosstalk is analyzed for different line lengths, line widths, and interconnect driver resistances. Considering the P/G noise, a shield line can degrade rather than enhance signal integrity due to increased P/G noise coupling on the victim line. A 2π RLC interconnect model is used to investigate the effects of both coupling capacitance and mutual inductance on the crosstalk noise. Physical spacing and shield insertion are compared in terms of the coupling noise on the victim line for several technology nodes. Boundary conditions are also provided to determine the effective range of spacing and shield insertion in the presence of P/G noise. Additionally, the effects of technology scaling on P/G noise and shielding efficiency are discussed, and related design tradeoffs are addressed.

Substrate and Ground Noise Interactions in Mixed-Signal Circuits

The interaction of the substrate with the inductive on-chip ground distribution network is analyzed in this paper. A transistor level approach is presented to illustrate the effects of the substrate on ground noise. The substrate can have a significant effect on ground noise due to the inductance of the ground lines. For a CMOS inverter, the substrate can reduce negative peak ground noise by 49% during the high-to-low output transition. The substrate, however, increases the positive peak ground noise by 72% during the low-to-high output transition. The effect of the substrate should therefore not be neglected if the inductance of the on-chip ground distribution network is non-negligible. Furthermore, conventional triangle or trapezoid type current demand estimations of the nonlinear circuits are shown to be significantly inaccurate if the ground lines exhibit inductive behavior.

Hardware Security Threats and Potential Countermeasures in Emerging 3D ICs

New hardware security threats are identified in emerging three-dimensional (3D) integrated circuits (ICs) and potential counter-measures are introduced. Trigger and payload mechanisms for future 3D hardware Trojans are predicted. Furthermore, a novel, network-on-chip based 3D obfuscation method is proposed to block the direct communication between two commercial dies in a 3D structure, thus thwarting reverse engineering attacks on the vertical dimension. Simulation results demonstrate that the proposed method effectively obfuscates the cross-plane communication by increasing the reverse engineering time by approximately 5× as compared to using direct through silicon via (TSV) connections. The proposed method consumes approximately one fifth the area and power of a typical network-on-chip designed in a 65 nm technology, exhibiting limited overhead.

Utilizing interdependent timing constraints to enhance robustness in synchronous circuits

Interdependent setup-hold times are exploited during the design process to improve the robustness of a circuit. Considering this interdependence only during static timing analysis (STA), as demonstrated in the previous work, is insufficient to fully exploit the capabilities offered by interdependence. This result is due to the strong dependence of STA results on the specific circuit, cell library, and operating frequency. Interdependence is evaluated in this paper for several technologies to determine the overall reduction in delay uncertainty rather than improvements in STA. Reducing delay uncertainty produces a more robust synchronous circuit. The increasing efficacy of interdependence in deeply scaled technologies is also demonstrated by investigating the effect of technology scaling on interdependent timing constraints.