Oliver Vojinovic

Version control in project-based learning

This paper deals with the development of a generalized model for version control systems application as a support in a range of project-based learning methods. The model is given as UML sequence diagram and described in detail. The proposed model encompasses a wide range of different project-based learning approaches by assigning a supervisory role either to instructor or students in different project stages. Different strategies for supervisor role assignment are given. Project duration, project milestones, as well as a number of team members are discussed in respect to project-based learning method that the proposed model supports. Possible implementations of different project-based learning approaches on the proposed model are demonstrated by setting the model parameters. Version control server security issues are discussed in the manner of implementation aspects of the proposed model. One of possible model implementations is evaluated in respect of cooperation on the test group of 21 students. Implementation details are presented and compared with other approaches. Mentoring and monitoring students efforts during the development by implementing proposed model with specific model settings introduces controlled cooperation with high clarity in evaluation of individual students work. Using open source version control software on Linux platform, with web interface package, we implemented a low-cost support for project-based learning.

Family of folded bit-serial multipliers

The synthesis of new family of folded bit-serial multipliers for integer multiplication is presented in this paper. Folding technique is applied to serial-parallel serial multiplier architecture. The resulting architecture can operate with operands of arbitrary length. In order to illustrate functionality of proposed architecture the preliminary results of FPGA implementation are given.

Folded bit-plane FIR filter architecture with changeable folding factor

The application of folding technique to the bit-plane systolic FIR filter architecture that enables the implementation of changeable folding factor onto the fixed size array is described in this paper. The transformation of original data flow graph (DFG) for bit-plane architecture that provides the successful application of the folding technique with changeable folding sets is presented. The involving of changeable folding sets in the synthesized folded architecture allows the reducing of folding factor according to the coefficient length increasing the throughput of the folded system.