Ivan Milentijevic

Version control in project-based learning

This paper deals with the development of a generalized model for version control systems application as a support in a range of project-based learning methods. The model is given as UML sequence diagram and described in detail. The proposed model encompasses a wide range of different project-based learning approaches by assigning a supervisory role either to instructor or students in different project stages. Different strategies for supervisor role assignment are given. Project duration, project milestones, as well as a number of team members are discussed in respect to project-based learning method that the proposed model supports. Possible implementations of different project-based learning approaches on the proposed model are demonstrated by setting the model parameters. Version control server security issues are discussed in the manner of implementation aspects of the proposed model. One of possible model implementations is evaluated in respect of cooperation on the test group of 21 students. Implementation details are presented and compared with other approaches. Mentoring and monitoring students efforts during the development by implementing proposed model with specific model settings introduces controlled cooperation with high clarity in evaluation of individual students work. Using open source version control software on Linux platform, with web interface package, we implemented a low-cost support for project-based learning.

The Design of Optimal Planar Systolic Arrays for Matrix Multiplication

Abstract The objective of this paper is to provide a systematic methodology for the design of space-time optimal pure planar systolic arrays for matrix multiplication. The procedure is based on data dependence approach. By the described procedure, we obtain ten different systolic arrays denoted as S 1 to S 10 classified into three classes according to interconnection patterns between the processing elements. Common properties of all systolic array designs are: each systolic array consists of n 2 processing elements, near-neighbour communications, and active execution time of 3 n − 2 time units. Compared to designs found in the literature, our procedure always leads to systolic arrays with optimal number of processing elements. The improvement in space domain is not achieved at the cost of execution time or PEs complexity. We present mathematically rigorous procedure which gives the exact ordering of input matrix elements at the beginning of the computation. Examples illustrating the methodology are shown.

Pedagogical agent in Multimedia Interactive Modules for Learning - MIMLE

Using new game-based learning systems in college education is neither an easy nor a simple task. The aim of such systems is to keep attention, teach students or assess their knowledge through a game. With the aim of keeping students attention through a game, in this paper we show the implementation of game-based learning systems with a pedagogical agent. We presents two models for assessing students knowledge used by a pedagogical agent which is a part of the new class of Multimedia Interactive Modules for Learning - MIMLE. One of the models is used for activating the agent. It is realized as a window of Help option and built in accordance to Marcov decision process theory (MDP). The basic goal of this mode is to determine the minimal intervention of the agent towards making the right direction concerning the studying process based on simulation learning. With the second, long-term model, we have assessed students knowledge in the current game level that is used to decide students should pass on to the next level of learning or if they should stay on the same level.

Configurable digit-serial convolver of type F

The semi-systolic architecture, known as design F, is used as a basic structure for synthesis of a digit-serial fault-tolerant convolver. The proposed convolver has the structure of a tree with connected leaves. Leaves are multiplier cells, while nodes are adder cells. The Diogenes approach is a well-known reconfiguration technique for structures with identical processing elements (PEs), and is accepted for reconfiguration of the proposed convolver. In order to apply the Diogenes approach to the proposed structure, we propose the modification of this approach which relates to involving PEs of two types. The proposed modification provides configuration of the convolver structure in a number of taps in the presence of faults, so the fault tolerance is achieved through dynamic reconfiguration.

Yield analysis of partial defect tolerant bit-plane array

Silicon complexity places long-stand paradigms at risk. Key concerns include increasing process variations, defect rates, infant mortality rates, and susceptibility to internal and external noises. These trends are likely to decrease functional yield. Fabrication of die with 100% working transistors and interconnections becomes prohibitively expensive. This paper examines the size and the position of the candidate part of the architecture for defect tolerance application, for the given topology and defect probability where yield can be improved in comparison to error tolerant design. In order to achieve the mentioned goal, we modified the existing mathematical description of yield by involving error tolerant concept introducing a function @C(@a) that models the topology of architecture. The evaluation is demonstrated on the bit-plane semi-systolic array, as a relatively complex array topology. The method that we hereby present for the chosen topology is described and proved in formal mathematical way, and it easily covers simpler topologies. It will be shown that partial involvement of defect tolerant design can significantly improve effective yield for defect rates which are common in nanotechnology.

Configurable folded array for FIR filtering

The synthesis of configurable bit-plane processing array for FIR filtering is described in this paper. Possibilities for configuration are explored and encompassed by application of folding technique. The proposed folded architecture supports on-the-fly configuration of number of taps and coefficient length. This is achieved by dynamic operations mapping on the different hardware units in array structure. Dynamic operations mapping, involved in application of folding technique, allows recognition of user defined parameters, such as number of coefficients and coefficient length on implemented array size. The architecture provides flexible computations and offers the possibility of increasing the folded system throughput, by reducing the number of operations performed on a single functional unit, at cost of decreasing the coefficient number or length. Effects of folding technique application to architecture configuration capabilities are presented. The configurable folded FIR filter synthesis process is presented in detail. The obtained folded system architecture is described by block diagram, DFG, functional block diagram and the data flow diagram. The method of operation and operations mapping on the processing units are described. The algorithms for data reordering are given. With the aim to illustrate the functionality, configuration capabilities, and trade-offs relating to occupation of the chip resources and achieved throughputs of synthesized folded architecture, we present results of FPGA prototyping. The proposed configurable folded array is used for H.264/AVC deblocking filter implementation with extremely low-gate count that is achieved at the cost of time, but the design meets the requirement for real-time deblocking in mobile embedded computing platforms.

Area-time tradeoffs in h.264/AVC deblocking filter design for mobile devices

H.264/AVC is a new international standard for the compression of natural video images, in which deblocking filter has been adopted to remove blocking artifacts. The deblocking filter is either time or area consuming system component. The goal of this paper is a design of area-time efficient H.264/AVC deblocking filter suitable for application in mobile devices. Area-time tradeoff is enabled by using configurable folded bit-plane filter as a core for deblocking filter implementation. Folded filter implementation parameters are obtained in the manner of achievement of minimal area consumption, keeping in mind throughput requirement in mobile devices. Systempsilas architecture is presented in detail, as well as the architecture of folded deblocking filter. With aim to illustrate functionality and tradeoffs related to occupation of chip resources and achieved throughputs we present results of FPGA prototyping. Proposed deblocking filter requires extremely low gate count still meeting the mobile application throughput requirements.

Error significance map for bit-plane FIR filtering array

Some applications require correct computation, while many others do not. Large domain where perfect functional performance is not always required is in multimedia and DSP systems. Relaxing the requirement of 100% correctness for devices and interconnections may dramatically reduce costs of manufacturing, verification, and testing. The goal of this paper is development of error significance map for bit-plane FIR filtering array. The map marks the part of the array that must be error-free in order to enable computing on the bit-plane array with acceptable results. In other words the array cells, out of the marked area, could produce errors, but without significant influence on the marked high order bits of the resulting word. The bit-plane array operates on a bit level and assumes accumulation throughout the array with sum and carry propagation. It means that derivation of the error significance map is not a trivial for design automation. In this paper we propose a rigorous mathematical path based on transitive closure that generates error significance map for the bit-plane array.

Run-Time Machine Learning for HEVC/H.265 Fast Partitioning Decision

A novel fast Coding Tree Unit partitioning for HEVC/H.265 encoder is proposed in this paper. This method relies on run-time trained neural networks for fast Coding Units splitting decisions. Contrasting to state-of-the-art solutions, this method does not require any pre-training and provides a high adaptivity to the dynamic changes in video contents. By an efficient sampling strategy and a multi-thread implementation, the presented technique successfully mitigates the computational overhead inherent to the training process on both the overall processing performance and on the initial encoding delay. The experiments show that the proposed method successfully reduces the HEVC/H.265 encoding time for up to 65% with negligible rate-distortion penalties.

Designing Intelligent Agent in Multilevel Game-Based Modules for E-Learning Computer Science Course

Nowadays, game-based learning environments are very common environments for studying major scientific fields such as mathematics, computer science, electronics and electrical engineering. This chapter presents a game-based modules system called the game-based modules (GBMs). It combines the characteristics of computer game elements with the existing interactive multimedia environments for learning mathematics, physics and electronics. This module presents a new type of game-learning environment for teaching units of Computer Science courses. Bearing in mind that the GBMs includes interactive tasks as a form of a multi-level approach to problem solving, we have also shown an approach to evaluating student’s knowledge necessary for upgrading him/her to the higher level of learning. To assess a student’s knowledge level needed for the next game level in the GBMs, we have developed an intelligent agent. This illustrates how intelligent agents and fuzzy logic can help increase the quality and quantity of the most important element of e-learning and that is making a decision. The results of student’s knowledge diagnosis by means of agent within the GBMs e-learning system demonstrate the possibility of applying the presented agent model in various game-based learning systems for the determination of the knowledge level performance. On the basis of the data obtained through the exams, as well as through the use of statistical reasoning methods, we have shown the efficiency of the GBMs in the learning process.