Vladimir Ciric

Version control in project-based learning

This paper deals with the development of a generalized model for version control systems application as a support in a range of project-based learning methods. The model is given as UML sequence diagram and described in detail. The proposed model encompasses a wide range of different project-based learning approaches by assigning a supervisory role either to instructor or students in different project stages. Different strategies for supervisor role assignment are given. Project duration, project milestones, as well as a number of team members are discussed in respect to project-based learning method that the proposed model supports. Possible implementations of different project-based learning approaches on the proposed model are demonstrated by setting the model parameters. Version control server security issues are discussed in the manner of implementation aspects of the proposed model. One of possible model implementations is evaluated in respect of cooperation on the test group of 21 students. Implementation details are presented and compared with other approaches. Mentoring and monitoring students efforts during the development by implementing proposed model with specific model settings introduces controlled cooperation with high clarity in evaluation of individual students work. Using open source version control software on Linux platform, with web interface package, we implemented a low-cost support for project-based learning.

Area-time tradeoffs in h.264/AVC deblocking filter design for mobile devices

H.264/AVC is a new international standard for the compression of natural video images, in which deblocking filter has been adopted to remove blocking artifacts. The deblocking filter is either time or area consuming system component. The goal of this paper is a design of area-time efficient H.264/AVC deblocking filter suitable for application in mobile devices. Area-time tradeoff is enabled by using configurable folded bit-plane filter as a core for deblocking filter implementation. Folded filter implementation parameters are obtained in the manner of achievement of minimal area consumption, keeping in mind throughput requirement in mobile devices. Systempsilas architecture is presented in detail, as well as the architecture of folded deblocking filter. With aim to illustrate functionality and tradeoffs related to occupation of chip resources and achieved throughputs we present results of FPGA prototyping. Proposed deblocking filter requires extremely low gate count still meeting the mobile application throughput requirements.

Error significance map for bit-plane FIR filtering array

Some applications require correct computation, while many others do not. Large domain where perfect functional performance is not always required is in multimedia and DSP systems. Relaxing the requirement of 100% correctness for devices and interconnections may dramatically reduce costs of manufacturing, verification, and testing. The goal of this paper is development of error significance map for bit-plane FIR filtering array. The map marks the part of the array that must be error-free in order to enable computing on the bit-plane array with acceptable results. In other words the array cells, out of the marked area, could produce errors, but without significant influence on the marked high order bits of the resulting word. The bit-plane array operates on a bit level and assumes accumulation throughout the array with sum and carry propagation. It means that derivation of the error significance map is not a trivial for design automation. In this paper we propose a rigorous mathematical path based on transitive closure that generates error significance map for the bit-plane array.

Coefficient bit reordering method for configurable FIR filtering on folded bit-plane array

The goal of this paper is development of coefficient bit reordering method for configurable FIR filtering that will enable correct mapping of operations onto functional units of folded bit-plane FIR filtering array, regardless to coefficient number and length. The reordering method is derived in mathematical form and used to synthesize a configurable hardware module that feeds folded array with coefficient bits in proper order. On-the-fly reconfiguration of filtering array is achieved by reconfiguration of hardware module that implements reordering algorithm. Possibilities for throughput increasing by reducing filtering parameters are explored. The derived module is able to handle feeding of folded bit-plane array with different number of coefficients and coefficient length, and it is able to increase the throughput of folded system in cases where filtering with reduced number of taps or coefficient length is performed.

Synthesis of folded fully pipelined bit-plane architecture

This paper describes the application of folding technique to the Bit-Plane systolic FIR filter Architecture (BPA). We present the transformation of original DFG (Data Flow Graph) that enables the application of folding technique and the synthesis of fully pipelined folded architecture. The array is restricted for the factor in, where in represents the coefficient length. The number of basic cells in target architecture is reduced to the number of basic cells in one plane of source architecture. Also, the total number of latches corresponds to the number of latches in one plane of the BPA. The hardware restriction is paid by decreasing of throughput for slightly more than in times.

Power consumption aware software architecture for M-health applications with adaptive security of network protocols

The goal of this paper is development of software architecture for mobile devices, which is able to trade-off between security levels and power consumption. The analysis of the influence of different security protocols on power consumption is given. The proposed architecture is described in detail. Three different security levels with corresponding cipher suites are proposed: low, medium and high. The architecture is implemented on Android platform. The difference in power consumptions of the cipher suites in high and low security/power profiles is around 8.2% for WiFi, and 9.6% for 3G network. In order to further reduce the power consumption during network communication, the delay between sending two successive packets is analyzed. The proposed architecture is capable of stalling packets and sending them in burst-mode, letting the network interface to stay in low-power mode for a longer period of time. The power consumption in this mode is reduced for additional 25%.

Sparse Matrix Multiplication on Dataflow Engines

In this paper, a novel architecture for sparse matrix multiplication is proposed. The architecture is suitable for implementation in specific environments such as dataflow engines. In order to avoid multiple streaming of elements from the host, we propose the architecture which buffers the elements from the input stream in on-chip memory in the form of pages. In the case of sparse matrices, the architecture processes only pages with non-zero elements. The proposed architecture allows replication of its blocks in order to parallelize the computation. The architecture is implemented on Maxeler dataflow engine based on Virtex 5 FPGA. The implementation results are given.

Tropical algebra based framework for error propagation analysis in systolic arrays

Nanotechnology is yet to come, but even now, in early stage of development it is clear that defect and fault levels will be much higher than current CMOS technology. The exact level of defect densities is unknown, but it is assumed that 1-15% on-chip resources will be defective. Novel techniques and architectures have to be devised in order for nanoelectronics to become a viable replacement for current VLSI processes. With defect rates for current VLSI processes in the range of 1 part per billion, manufacturers can afford to discard any chip that is found to be defective. However, in order to increase fabrication yield, nanotechnology requires extensive and computationally demanding analysis of defect significance. In order to simplify the analysis, in this paper we propose a mathematical framework based on tropical algebra for circuit analysis. It is more descriptive and convenient to use in graph analysis than traditional algebra. In tropical algebra, we will derive a simple iterative algorithm for error propagation analysis of systolic arrays. It will be shown that the computational complexity of the proposed algorithm is reduced from O(T^3) to O(T^2), where T is the number of array cells. An example of tropical algebra analysis and design of partially defect tolerant hexagonal systolic multiplier will be given, too.

Trading defect tolerance for chip area in nanotecnology implementations of systolic arrays

New self-assembling techniques used to build nano-scale architecture prototypes have a drawback of being prone to defects and transient faults. Fault and defect tolerance techniques will be crucial to the use of nano-electronics in the future. However, these techniques usually introduce a significant hardware overhead. In these paper we are proposing a method for trading an architecture tolerance on fabrication defects for chip area. The method will be presented using an architecture with generic topology and illustrated on the example of partially defect tolerant bit-plane semi-systolic array. In order to illustrate the method the results of FPGA implementation of completely fault tolerant bit-plane array, and partially fault tolerant bit-plane array will be given.

Cost estimation of nanoscale partial defect tolerant arrays

High defect rates are common in nanotechnology and fabrication has to deal with increasing variations and percent of mortality rates. Qualitative changes are introduced in circuit design to make nanoscale architectures less prone to defects. Fault tolerant techniques will be crucial to the use of nano-electronics in the future. On architectural level, partial defect tolerant design can be a candidate method to decrease overall fabrication costs. The goal of this paper is to estimate costs of nanotechnology fabrications of partial defect tolerant systolic arrays with different topologies. With aim to investigate the possibilities for nanoscaling of partial defect tolerant arrays with different topologies the yield analysis procedure will be given. We will consider 1D systolic array for matrix-vector multiplication and 2D bit-plane semi-systolic array. Fabrication cost savings for partial defect tolerant nanoscale designs will be analytically obtained and illustrated on FPGA implementation of the arrays.