Olivier Toublan

Phase aware proximity correction for advanced masks

In this paper we describe the use of sparse aerial image simulation coupled with process simulation, using the variable threshold resist (VTR) model, to do optical and process proximity correction (OPC) on phase shift masks (PSM). We will describe the OPC of PSM, including attenuated PSM, clear field PSM, and double exposure PSM. We will explain the method used to perform such OPC and show examples of critical dimension control improvements generated from such a technique. Simulations, PSM assignment and model based OPC corrections are performed with Calibre Workbench, Calibre DRC, Calibre PSMgate and Calibre OPCpro tools from Mentor Graphics. In conclusion we will show that PSM techniques need to be corrected by a phase aware proximity correction tool in order to achieve both pattern fidelity as well as small feature size on the wafer in a production environment.

Model-assisted double dipole decomposition

Double dipole processes in general have been considered for full Manhattan design styles. However, with the assistance of current model-based OPC tools and high-resolution optical systems, it is possible to analyze the requirements for all angle designs. When angled features present in the design layout are located in regions where only connectivity and not CD control is critical, the method generates an acceptable solution for a given set of optical conditions. The present methodology investigates the use of selective edge biases for clear-field double dipole decomposition. Such an approach is based on the double exposure nature of the method. In full Manhattan designs, two different contrast values are associated to every edge, and in general one is higher than the other. On the contrary, angled edges may have the same contrast depending on the shape of the pupil and local proximity environment. This method maximizes the overall contrast of the layout by creating selective feature biases. These biases are placed in the non-optimal optical direction and protect the regions that have a higher contrast in the complementary dipole direction. The initial decomposition generates two masks in which a maximum global contrast function is maximized. This initial decomposition is later fed to a two-layer model based correction. The final result is analyzed in terms of contrast, pattern fidelity and focus dependence in order to determine the feasibility of printing Manhattan and angled features using a double dipole approach for sub 100 nm processes.

Layout compensation for EUV flare

Flare has been noted as a significant concern for Extreme Ultraviolet (EUV) Lithography. Recent results on prototype tools have shown flare on the order of 40% in extreme cases. This is far from the ideal result. Flare compensation for EDA software tools such as Mentor Graphics’ Calibre RET Suite has been developed, and can be used to compensate density dependent fluctuations in conventional DUV lithography. This can be as simple as making corrections using rules for the variations of isolated and dense lines in an environment with prescribed flare, or a more complex correction incorporating flare into model-based OPC. Flare in EUV systems, however, has been shown to be non-uniform, with complex variations. In this presentation, we describe this flare correction technique and explore the correction of typical IC layouts that would be required to compensate for reported EUV flare values.

High accuracy 65nm OPC verification: full process window model vs. critical failure ORC

It is becoming more and more difficult to ensure robust patterning after OPC due to the continuous reduction of layout dimensions and diminishing process windows associated with each successive lithographic generation. Lithographers must guarantee high imaging fidelity throughout the entire range of normal process variations. The techniques of Mask Rule Checking (MRC) and Optical Rule Checking (ORC) have become mandatory tools for ensuring that OPC delivers robust patterning. However the first method relies on geometrical checks and the second one is based on a model built at best process conditions. Thus those techniques do not have the ability to address all potential printing errors throughout the process window (PW). To address this issue, a technique known as Critical Failure ORC (CFORC) was introduced that uses optical parameters from aerial image simulations. In CFORC, a numerical model is used to correlate these optical parameters with experimental data taken throughout the process window to predict printing errors. This method has proven its efficiency for detecting potential printing issues through the entire process window [1]. However this analytical method is based on optical parameters extracted via an optical model built at single process conditions. It is reasonable to expect that a verification method involving optical models built from several points throughout PW would provide more accurate predictions of printing errors for complex features. To verify this approach, compact optical models similar to those used for standard OPC were built and calibrated with experimental data measured at the PW limits. This model is then applied to various test patterns to predict potential printing errors. In this paper, a comparison between these two approaches is presented for the poly layer at 65 nm node patterning. Examples of specific failure predictions obtained separately with the two techniques are compared with experimental results. The details of implementing these two techniques on full product layouts are also included in this study.

Logic design for printability using OPC methods

The steps that create physical shape data in a typical logic device design-to-reticle flow are cell layout, place and route, tapeout, OPC or RET, data fracture, and reticle build. Here, we define OPC as the transformation of reticle data to compensate for lithographic and process distortions so that the final wafer pattern is as close to the target pattern-the designed layout-as possible. We define RETs as the general class of transformations for reticle data that aim to improve the patterning process window; therefore, OPC is a subset of RET. DFM is traditionally considered to be implemented at the cell layout or routing stages of this flow. Examples include the optimization of a layout based on critical-defect area, the addition of redundant contacts and vias, wire spreading, upsizing of metal landing pads, and the addition of dummy metal tiles to improve the planarity after chemical-mechanical planarization (CMP). We presented a detailed analysis of these techniques in an earlier work. In contrast, this article analyzes the possibility of extending these traditional methods into the OPC stage and introduces new post-tapeout RET methods for improving printability.

Design verification flow for model-assisted double-dipole decomposition

Double-exposure techniques are currently being explored as alternatives to the low k1 problem that arises form the current absence of next-generation lithography (NGL) tools. Off-axis illumination conditions such as annular, used in conjunction with binary chrome masks are able to resolve features as small as 100nm. However, these off-axis approaches only improve a limited set of pitches. While certain features on the layout are enhanced, others loose contrast and cannot be imaged properly. Dipole illumination is the extreme off-axis case, but this high/low contrast problem is lessened by a double exposure approach. Double exposure corrections require a global optimization of tow masks. As is the case with any multi-dimensional problem, current model OPC algorithms are able to locally optimize the solution, but it is difficult to guarantee a global optimal set. Including in the correction mask-manufacturing constraints can reduce this apparent problem. By limiting the number of local optimal states accessible to the convergence criterion, it is possible to arrive at a better solution. This solution is lithographically correct and easier to manufacture. In this work we preset a data flow using models created previously for a model-assisted dipole decomposition to rank different approaches based on final image contrast, pattern fidelity and focus dependency. We also provide insights on how angled features can be successfully imaged under a double dipole approach, showing how such features need to be studied form an image formation point of view, not under simple geometric principles that rule out the presence of angled features.

Fully automatic side lobe detection and correction technique for attenuated phase-shift masks

Using a new functionality of the Calibre PrintImage tool, a method for side lobe correction is presented. A full chip aerial image mapping is first obtained and then analyzed to detect and output polygons corresponding to chip areas where the aerial image intensity is above a user set threshold. Using state of the art DRC tool and associated RET software from Mentor Graphics we are able to propose a completely automated flow for side lobe detection and correction. Mask manufacturing complexity can also be taken into consideration using geometrical constraints similar to those used for scattering bars, such as minimum length, minimum width and minimum space to main features.

Investigation of model-based physical design restrictions (Invited Paper)

As lithography and other patterning processes become more complex and more non-linear with each generation, the task of physical design rules necessarily increases in complexity also. The goal of the physical design rules is to define the boundary between the physical layout structures which will yield well from those which will not. This is essentially a rule-based pre-silicon guarantee of layout correctness. However the rapid increase in design rule requirement complexity has created logistical problems for both the design and process functions. Therefore, similar to the semiconductor industrys transition from rule-based to model-based optical proximity correction (OPC) due to increased patterning complexity, opportunities for improving physical design restrictions by implementing model-based physical design methods are evident. In this paper we analyze the possible need and applications for model-based physical design restrictions (MBPDR). We first analyze the traditional design rule evolution, development and usage methodologies for semiconductor manufacturers. Next we discuss examples of specific design rule challenges requiring new solution methods in the patterning regime of low K1 lithography and highly complex RET. We then evaluate possible working strategies for MBPDR in the process development and product design flows, including examples of recent model-based pre-silicon verification techniques. Finally we summarize with a proposed flow and key considerations for MBPDR implementation.

Evaluation of OPC mask printing with a raster scan pattern generator

MEBESR 50 kV mask pattern generators use Raster GraybeamTM writing, providing an effective grid that is 32X finer than the print grid. The electron beam size and print pixel size are variable between 60 nm and 120 nm, allowing a tradeoff between resolution and write time. Raster scan printing optimizes throughput by transferring precisely the amount of data to the mask that is consistent with the chosen resolution. As with other raster output devices, mask write times are not affected by pattern complexity. This paper examines the theoretical performance of Raster Graybeam for model-based optical proximity correction (OPC) patterns and provides examples of mask patterning performance. A simulation tool is used to model the MEBES eXaraTM system writing strategy, which uses four writing passes, interstitial print grids, offset scans, and eight dose levels per pass. It is found that Raster Graybeam produces aerial image quality equivalent to the convolution of the input pattern data with a Gaussian point spread function. Resolution of 90 nm is achieved for equal lines and spaces, supporting subresolution assist features. Angled features are a particular strength of raster scan patterning, with feature quality and write time that are independent of feature orientation.

Phase and transmission errors aware OPC solution for PSM: feasability demonstration

To follow the SIA roadmap, lithographers must deal everyday with the bad effects of a low-kl lithography transfer process. One of the ways to reduce the pressure associated with such low-kl values is to use Alternating Phase Shift Masks (henceforth “Alt-PSM”). Unfortunately, Alt-PSM also has some drawbacks, such as transmission imbalance between the phase shifted and non-phase shifted areas, and aspect ratio phase etch depth variation resulting from the mask etching process. Moreover, fast two-dimensional simulators that are commonly used in resolution enhancement simulation are unable to directly predict these inherently three-dimensional effects. We demonstrate a general approach to simulate and correct these effects in large circuit designs by combining accurate mask representation with Optical and Process Correction (“OPC”). Using a DRC tool, geometry in the input circuit design is partitioned based on size and shape. Guided by accurate three-dimensional simulations or empirical data, these partitions may be classified and assigned different phases and transmission values to more realistically simulate the mask. By using this more accurate mask representation in our integrated OPC tool, Calibre OPCPro, we are able to correct designs for these three-dimensional mask effects as well as for conventional proximity effects.