Olli Lehtoranta

A parallel MPEG-4 encoder for FPGA based multiprocessor SoC

A parallel MPEG-4 simple profile encoder for FPGA based multiprocessor system-on-chip (SoC) is presented. The goal is a computationally scalable framework independent of platform. The scalability is achieved by spatial parallelization where images are divided to horizontal slices. Slice coding tasks are mapped to the multiprocessor consisting of four soft-cores arranged into master-slave configuration. Also, the shared memory model is adopted where large images are stored in shared external memory while small on-chip buffers are used for processing. The interconnections between memories and processors are realized with our HIBI network. Our main contributions are the scalable encoder framework as well as methods for coping with limited memory of FPGA. The current software only implementation processes 6 QCIF frames/s with three encoding slaves. In practice, speed-ups of 1.7 and 2.3 have been measured with two and three slaves, respectively. FPGA utilization of current implementation is 59% requiring 24 207 logic elements on Altera Stratix EP1S40.

Scalable MPEG-4 encoder on FPGA multiprocessor SOC

High computational requirements combined with rapidly evolving video coding algorithms and standards are a great challenge for contemporary encoder implementations. Rapid specification changes prefer full programmability and configurability both for software and hardware. This paper presents a novel scalable MPEG-4 video encoder on an FPGA-based multiprocessor system-on-chip (MPSOC). The MPSOC architecture is truly scalable and is based on a vendor-independent intellectual property (IP) block interconnection network. The scalability in video encoding is achieved by spatial parallelization where images are divided to horizontal slices. A case design is presented with up to four synthesized processors on an Altera Stratix 1S40 device. A truly portable ANSI-C implementation that supports an arbitrary number of processors gives 11 QCIF frames/s at 50 MHz without processor specific optimizations. The parallelization efficiency is 97% for two processors and 93% with three. The FPGA utilization is 70%, requiring 28 797 logic elements. The implementation effort is significantly lower compared to traditional multiprocessor implementations.

Detecting corrupted intra macroblocks in H.263 video

Corrupted low frequency data of intra coded macroblocks can significantly degrade quality of video in error prone wireless networks. Therefore, a new method for detecting the corrupted blocks is presented. The method exploits temporal smoothness of video by computing the absolute difference between subsequent video frames. A threshold function is used to highlight the block differences, and a heuristic is developed to detect the corrupted blocks. The proposed method is evaluated with our wireless video simulator, which shows that the method substantially improves image quality of video conferencing sequences in presence of transmission errors. In addition, the method is compared to average intersample difference across the block boundaries (AIDB) algorithm whose performance is shown to be more sensitive to selection of correct threshold values than the proposed method.

Real-time H.263 encoding of QCIF-images on TMS320C6201 fixed point DSP

In this paper a real-time video encoder following ITU-T H.263 recommendation is described and relative computational loads of various encoding phases are evaluated. The current implementation shows that QCIF size (176/spl times/144) images can be coded in real-time by TMS320C6201 when computationally light motion estimation routines and basic H.263 coding mode is used. The real-time performance can be achieved using C-code and optimizing some key functions like SAD (sum of absolute difference) with linear assembler. In addition, careful memory management design for program code and application data is required. With the presented coding scheme, up to 29 fps can be achieved.

Algorithmic optimization of H.264/AVC encoder

Several platform independent optimizations for a baseline profile H.264/AVC encoder are described. The optimizations include adaptive diamond pattern based motion estimation, fast sub-pel motion vector refinement and heuristic intra prediction. In addition, loop unrolling, early out thresholds and adaptive inverse transforms are used. An experimental complexity analysis is presented studying effect of optimizations on the encoding frame rate on the AMD Athlon processor. Trade-offs in rate-distortion performance are also measured. Compared to a public reference encoder, speed-ups of 4-8 have been obtained with 0.6-0.8 dB loss in image quality. In practice, our software only H.264 encoder achieves an encoding rate of 86 QCIF frames/s that is well above real-time limits.

Complexity analysis of spatially scalable MPEG-4 encoder

Computational complexity of MPEG-4 encoder supporting spatial scalability is presented. The encoder is partitioned into atomic functions whose complexities are estimated in terms of millions of RISC like operations per second (MOPS). A detailed listing of arithmetic, logic and control flow operations is given. The complexity estimates are used to identify computationally the most demanding encoding tasks. The results indicate that approximately 6600 RISC MOPS is required to encode CIF/4CIF-sized video layers while using frame rate of 30 frames/s and a low-complexity motion estimation algorithm. Furthermore, encoding both spatial layers with the new H.264/AVC causes computational load of 27000 RISC MOPS.

Video transfer control protocol for a wireless video demonstrator

Real-time streaming video is expected to emerge as a key service in different telecommunications systems, including wireless networks. This paper presents the functionality and implementation of the wireless Video Control Protocol (VCP). The protocol has been implemented for developing the functionality for real-time video stream transmission over heterogeneous wireless network technologies. VCP is embedded into a wireless video demonstrator. The demonstrator consists of Windows NT hosts containing a real-time H.263 encoder, video stream parsing functionality, and several network connections, such as wireless LAN, Bluetooth and GSM data. The protocol contains functionality for protecting the video stream transfer and adapting different network technologies together.

Impact of Shared Instruction Memory on Performance of FPGA-based MP-SoC Video Encoder

The impact of shared instruction memory on performance is measured and analyzed for an FPGA-based multiprocessor system-on-chip (MP-SoC) with an MPEG-4 video encoding application. Our MP-SoC architecture allows arbitrary scaling of the number of synthesized processors and includes a monitoring unit for memory transfers. Based on the measurements with up to four processors on Altera Stratix 1S40, an estimate of the effect of the shared memory for larger configurations is presented. The shared instruction memory is shown to be area-efficient and sufficient in performance for configurations up to five processors, as the drop in encoded video frame rate stays below one compared to distributed instruction memory organization

Parallel implementation of H.263 encoder for CIF-sized images on quad DSP system

A parallel implementation of H.263/MPEG-4 video encoder for Common Intermediate Format (CIF, 352/spl times/288) pictures is presented. The implementation runs on Hunt Engineerings Hepc/spl delta/ DSP-carrier featuring four TMS320C6201 ICs. The experimental results show real-time encoding speed of 30 fps has been reached using configuration of a master and two slave encoding DSPs. In addition, DSP-to-DSP link requirements, image quality vs. bit rate, scalability and frame rate performance are measured and analyzed.

Feasibility study of a real-time operating system for a multichannel MPEG-4 encoder

Feasibility of DSP/BIOS real-time operating system for a multi-channel MPEG-4 encoder is studied. Performances of two MPEG-4 encoder implementations with and without the operating system are compared in terms of encoding frame rate and memory requirements. The effects of task switching frequency and number of parallel video channels to the encoding frame rate are measured. The research is carried out on a 200 MHz TMS320C6201 fixed point DSP using QCIF (176x144 pixels) video format. Compared to a traditional DSP implementation without an operating system, inclusion of DSP/BIOS reduces total system throughput only by 1 QCIF frames/s. The operating system has 6 KB data memory overhead and program memory requirement of 15.7 KB. Hence, the overhead is considered low enough for resource critical mobile video applications.