Oluwafemi O. Ogunsola

Optical transmission of polymer pillars for chip I/O optical interconnections

In the pursuit of high-density wafer-level input-output optical interconnections, microscopic polymer pillars have recently been fabricated. The optical performance of these pillars is critical for their potential application to gigascale integration. In the present work, the optical transmission of these pillars is analyzed and measured. It is shown that these polymer pillars act as precision many-moded waveguides, thus, verifying the cross-sectional uniformity, smoothness of surfaces, and optical quality of the material.

Chip-level waveguide-mirror-pillar optical interconnect structure

Waveguides, mirrors, and polymer pillars can be integrated together to provide optical interconnects to the chip level. Total internal reflection in the polymer pillar provides a high level of spatial confinement of the light. The metallized mirror terminating the waveguide may be at 45deg or at a nearby angle such as 54.74deg (anisotropically etched silicon) and produce nearly equal coupling efficiencies. For a polymer waveguide, a gold mirror, and a polymer pillar of the dimensions fabricated, the simulated coupling efficiencies are 80.7% or 0.93 dB (45deg mirror) and 82.5% or 0.84 dB (54.74deg mirror), respectively. These simulations together with the fabrication and testing of a 54.74deg mirror configuration demonstrates the viability of the waveguide-mirror-pillar structure, its insensitivity to mirror angle, and its compatibility with current substrate fabrication technologies

Sea of polymer pillars: dual-mode electrical-optical Input/Output interconnections

Sea of Polymer Pillars (SoPP) provides highly integrated wafer-level optical and electrical Input/Output (I/O) interconnections for the die-to-module/board interconnection level. The advantages of this integrated interconnection technology include dual-mode I/O interconnections, high I/O density (>10/sup 5//cm/sup 2/), high performance, compliant electrical and optical interconnects, ease of assembly, wafer-level test compatibility, and ease of fabrication. The purpose of this paper is to extend the work developed by describing SoPP configurations, fabrication, and measurements.

Optical-fiber-to-waveguide coupling using carbon-dioxide-laser-induced long-period fiber gratings

Optical fibers are expected to play a role in chip-level and board-level optical interconnects because of limitations on the bandwidth and level of integration of electrical interconnects. Therefore, methods are needed to couple optical fibers directly to waveguides on chips and on boards. We demonstrate optical-fiber-to-waveguide coupling using carbon-dioxide laser-induced long-period fiber gratings (LPFGs). Such gratings can be written in standard fiber and offer wavelength multiplexing-demultiplexing performance. The coupler fabrication process and the characterization apparatus are presented. The operation and the wavelength response of a LPFG-based optical-fiber-to-waveguide directional coupler are demonstrated.

Optical Through-Wafer Interconnects for 3D Hyper-Integration

In this paper, we present the design, fabrication, and demonstration of optical through-wafer interconnects (TWIs). The interconnects were built using standard CMOS and MEMS fabrication processes

Electrical and Optical Chip I/O Interconnections for Gigascale Systems

This paper describes fully compatible, high-density, electrical, and optical chip input/output (I/O) interconnect networks for gigascale systems. All optical I/O interconnects are based on the use of low-loss microscopic polymer pins (pillars). Their compatibility with electrical solder-bump fabrication and assembly are demonstrated. Moreover, we describe the use of metal-coated polymer pins to provide both an electrical path and an optical path between the chip and the substrate. Such I/O interconnects are called dual-mode I/Os. The tradeoffs between the electrical resistance and mechanical compliance of the dual-mode pins are reported. Moreover, the minimum thickness of metal needed to enable each I/O to operate at its electrical bit-rate limit is derived. A chip containing dual-mode I/Os is assembled on a substrate containing electrical and optical interconnects and demonstrates the dual-mode functionality of the I/Os. Dual-mode polymer pins that are 55 mum in diameter and 110 mum in height are measured to have an electrical resistance of approximately 50 mOmega and attenuate the optical intensity by less than 0.15 dB (632.8-nm wavelength). The use of an optical-bonding polymer is shown to improve optical coupling efficiency by up to 2 dB. Lateral and vertical compliance measurements of the polymer pin are also reported.

Probe Module for Wafer-Level Testing of Gigascale Chips With Electrical and Optical I/O Interconnects

The bandwidth provided by optical interconnects makes them an attractive solution for chip-to-package and chip-to-chip communications. In such systems, chips will have optical I/O interconnects fabricated alongside their conventional electrical counterparts. Virtually no work has been previously reported relating to the testing of such chips at the wafer-level. The requirements for probe hardware needed to achieve this are identified, and probe module configurations based on these requirements are presented. A high-density micro-opto-electro-mechanical-systems (MOEMS)-based probe substrate prototype for interfacing with chips having electrical and optical polymer pillar-based I/Os has been designed, and built using microfabrication techniques. Successful probing of an array of polymer pillar-based optical I/Os is reported.Copyright

Dual-mode electrical-optical flip-chip I/O interconnects and a compatible probe substrate for wafer-level testing

We describe low cost compatible electrical and optical flip-chip I/O interconnects to leverage the performance requirements of future high-performance chips. Metal-clad polymer pins are fabricated and assembled to demonstrate chip-to-substrate electrical and optical interconnection. In order to address the complexity of wafer-level testing, a probe substrate designed to interface with the metal-clad polymer pin I/O interconnects is fabricated and demonstrated. The demonstration of these two distinct, yet highly related, advances (novel I/O and compatible probe substrate) addresses some of the key daunting problems facing the semiconductor industry

Polymer Pillars as Optical I/O for Gigascale Chips using Mirror-Terminated Waveguides

Polymer pillars are chip-level optical I/Os that provide spatial confinement of light propagating between a chip and a board/substrate. The integration of polymer pillars and mirror-terminated waveguides is presented. Pillars are fabricated directly above the metallized anisotropically-etched silicon sidewalls that terminate the waveguides. The mirror angle is 54.74deg, yet the presence of the pillar produces a 90deg bending of the light. Enabled by mirror-terminated waveguides, polymer pillars represent a promising optical I/O technology for GSI